datacnt.v

fpga开发pci的verilog

module datacnt(	
			clk,
			rst,
			r_ram_rdb,	
			r_ram_rab,	
			r_req,

			s_ram_wdb,
			fifo_wen,
			cmd,
			cmdack,
			addr,
			datain,
			dataout,			
			
			start_read,
			interrupt,
			rdusedw,
			wrusedw,
			s_fifo_rst
		    );
//--------------------ports--------------------
input			clk,rst;
input	[31:0]	r_ram_rdb;
input			r_req;
input			start_read;
input	[10:0] rdusedw;
input	[10:0] wrusedw;
input 			cmdack;

output	[10:0]	r_ram_rab;
output			interrupt;
output			fifo_wen;

output	[2:0]	cmd;
output	[20:0]	addr;
output	[31:0]	datain,s_ram_wdb;
input	[31:0]	dataout;
output			s_fifo_rst;

//---------port variables declaration-----------
wire	[31:0]	dataout;
reg				interrupt;
reg				s_req;
reg		[2:0]	cmd;
reg		[20:0]	addr;
reg		[31:0]	s_ram_wdb;
wire	[31:0]	datain;
wire			fifo_wen;
reg				s_enable;
reg		[20:0]	STATE;
reg		[7:0]	Burst_cnt;
reg		[1:0]	RCDCL_CNT;
reg				s_fifo_rst;
//----------------------------------------------
// State parameters used in MAIN  STATE MACHINE
parameter 
	IDLE			=21'b0_0000_0000_0000_0000_0001,//0
	PRECHARGE		=21'b0_0000_0000_0000_0000_0010,//1
	PRECHARGE_ACK	=21'b0_0000_0000_0000_0000_0100,//2   
	LOAD_MR			=21'b0_0000_0000_0000_0000_1000,//3
	LOAD_MR_ACK		=21'b0_0000_0000_0000_0001_0000,//4
	LOAD_R2			=21'b0_0000_0000_0000_0010_0000,//5
	LOAD_R2_ACK		=21'b0_0000_0000_0000_0100_0000,//6
	LOAD_R1			=21'b0_0000_0000_0000_1000_0000,//7
                          
	IDLE_WR			=21'b0_0000_0000_0001_0000_0000,//8   
	PAGE_WRITE		=21'b0_0000_0000_0010_0000_0000,//9
	BURST_WRITE		=21'b0_0000_0000_0100_0000_0000,//10
	BT_W			=21'b0_0000_0000_1000_0000_0000,//11
	WAIT_ACK_W_T	=21'b0_0000_0001_0000_0000_0000,//12
                         
	PAGE_READ		=21'b0_0000_0010_0000_0000_0000,//13
	BURST_READ		=21'b0_0000_0100_0000_0000_0000,//14
	BT				=21'b0_0000_1000_0000_0000_0000,//15
	LAST_DATA		=21'b0_0001_0000_0000_0000_0000,//16
	CLOSE_PAGE_W	=21'b0_0010_0000_0000_0000_0000,//17
	REFRESH_W       =21'b0_0100_0000_0000_0000_0000,//18
	CLOSE_PAGE_R    =21'b0_1000_0000_0000_0000_0000,//19
	REFRESH_R       =21'b1_0000_0000_0000_0000_0000;//20
	
parameter	
	NOP      		=3'b000,
	READA    		=3'b001,
	WRITEA   		=3'b010,
	ARF      		=3'b011,
	PRECHRG  		=3'b100,
	LOAD_MODE		=3'b101,
	LOAD_REG1 		=3'b110,
	LOAD_REG2 	 	=3'b111;

parameter RCD='d3,CL='d3,BL='d512;
//------------------------------------------------------------
//generate the cmd to the sdr_sdram_controller
always @ (STATE)
case(STATE)    
	PRECHARGE:		cmd = PRECHRG;
	LOAD_MR:		cmd = LOAD_MODE;
	LOAD_R2:		cmd = LOAD_REG2;
	LOAD_R1:		cmd = LOAD_REG1;
	PAGE_WRITE:		cmd = WRITEA;
	BT_W:			cmd = PRECHRG;
	CLOSE_PAGE_W:	cmd = PRECHRG;
	CLOSE_PAGE_R:	cmd = PRECHRG;
	PAGE_READ:		cmd = READA;
	BT:				cmd = PRECHRG;
	REFRESH_W:		cmd = ARF;
	REFRESH_R:		cmd = ARF;
	default:		cmd = NOP;
endcase
//------------------------------------------------------------
//transfer the data bus
always @ (posedge clk) 	
	s_ram_wdb[31:0] <= dataout[31:0];

assign	datain[31:0] = r_ram_rdb[31:0];
//------------------------------------------------------------
reg	r_req_reg;
always @ (posedge clk)
	r_req_reg <= r_req;
//------------------------------------------------------------
reg	STATE12_reg,STATE16_reg,STATE8_reg,STATE19_reg;

always @ (posedge clk) begin
	STATE12_reg <= STATE[12];
	STATE16_reg <= STATE[16];
	STATE8_reg  <= STATE[8];
	STATE19_reg <= STATE[19];
end

//------------------------------------------------------------
//generate the send wen signal 
assign fifo_wen = s_enable;
//-------------------------------------------------------------
//dpram read addr			
reg		[9:0]	r_ram_rab_reg;
reg				r_ram_rab_hbit;
wire	[10:0]	r_ram_rab = {r_ram_rab_hbit,r_ram_rab_reg};

always @ (posedge clk or negedge rst)
	if(!rst)
		r_ram_rab_reg <= 10'b0;
	else if(STATE12_reg && (r_ram_rab_reg == 'd511))//'d222
		r_ram_rab_reg <= 10'b0;
	else if((STATE[9] & cmdack) | STATE[10]) 
		r_ram_rab_reg <= r_ram_rab_reg + 1'b1;
	else
		r_ram_rab_reg <= r_ram_rab_reg;
	
	
always @ (posedge clk or negedge rst)
	if(!rst)
		r_ram_rab_hbit <= 1'b0;
	else if(STATE12_reg && (r_ram_rab_reg == 'd511))//'d222
		r_ram_rab_hbit <= ~r_ram_rab_hbit;
	else
		r_ram_rab_hbit <= r_ram_rab_hbit;
		
//---------------------------------------------------------------------
//sdram write addr
/*
reg		[7:0]	s_ram_wab_reg;
reg				s_ram_wab_hbit;
wire	[8:0]	s_ram_wab = {s_ram_wab_hbit,s_ram_wab_reg};

always @ (posedge clk or negedge rst)
	if(!rst)
		s_ram_wab_reg <= 8'b0;
	else if(s_enable)
		s_ram_wab_reg <= s_ram_wab_reg + 1'b1;
	else
		s_ram_wab_reg <= 8'b0;

always @ (posedge clk or negedge rst)
	if(!rst)
		s_ram_wab_hbit <= 1'b0;
	else if(STATE19_reg & cmdack)
		s_ram_wab_hbit <= ~s_ram_wab_hbit;
//---------------------------------------------------------------------	
*/
//*****************************************************************************//
//sdram write addr
reg	[10:0]	w_page;
reg	w_ba0;
wire	[1:0]	w_ba = {1'b0,w_ba0};

always @ (posedge clk or negedge rst)
	if(!rst)
		w_page <= 11'b0;
	else if(STATE12_reg && (w_page=='d1024))
		w_page <= 11'b0;
	else if(STATE12_reg)
		w_page <= w_page + 1'b1;

always @ (posedge clk or negedge rst)
	if(!rst)
		w_ba0 <= 1'b0;
	else if(STATE12_reg && (w_page=='d1024))
		w_ba0 <= ~w_ba0;
	
//****************************************************************************//
//****************************************************************************//
//sdram read addr
reg	[10:0]	r_page;
reg	r_ba0;
wire	[1:0]	r_ba = {1'b0,r_ba0};

always @ (posedge clk or negedge rst)
	if(!rst)
		r_page <= 11'b0;
	else if(STATE16_reg && (r_page=='d1024))
		r_page <= 11'b0;
	else if(STATE16_reg)//(STATE[19] & cmdack)
		r_page <= r_page + 1'b1;	

always @ (posedge clk or negedge rst)
	if(!rst)
		r_ba0 <= 1'b0;
	else if(STATE16_reg && (r_page=='d1024))
		r_ba0 <= ~r_ba0;
	
//********************************************************************************//
//********************************************************************************//				
//the state machine
always @(posedge clk or negedge rst)
begin
	if(!rst) begin
        STATE		<=	IDLE;
		s_enable	<=	1'b0;
        RCDCL_CNT	<= 	2'b0;
        Burst_cnt	<= 	8'b0;
	end

	else case(STATE)
	IDLE:								//STATE	0
		if(start_read)
			STATE<=PRECHARGE;
		else
			STATE<=IDLE;
//-------------------------------Initialization----------------------------------			
	PRECHARGE:							//STATE	1
		if(cmdack)
			STATE<=PRECHARGE_ACK;
		else
			STATE<=PRECHARGE;
			
	PRECHARGE_ACK:						//STATE	2
		STATE<=LOAD_MR;
			
	LOAD_MR:							//STATE	3
		if(cmdack)  
			STATE<=LOAD_MR_ACK;
		else
			STATE<=LOAD_MR;
			
	LOAD_MR_ACK:						//STATE	4
		STATE<=LOAD_R2;
			
	LOAD_R2:							//STATE	5
		if(cmdack)
	 		STATE<=LOAD_R2_ACK;
		else
			STATE<=LOAD_R2;
			
	LOAD_R2_ACK:						//STATE	6
		STATE<=LOAD_R1;
	
	LOAD_R1:							//STATE	7
		if(cmdack)
			STATE<=IDLE_WR;
		else
			STATE<=LOAD_R1;
//-------------------------------page write burst----------------------------------	
	IDLE_WR: begin                		//STATE	8
		if(r_req_reg)
			STATE<=PAGE_WRITE;
		else if(s_req && (w_ba0 != r_ba0))
			STATE<=PAGE_READ;
		else
			STATE<=IDLE_WR;
		end
		
	PAGE_WRITE: 						//STATE	9
		if(cmdack) begin
			STATE		<=	BURST_WRITE; 
			Burst_cnt	<=	8'b0;
			end
		else
			STATE<=PAGE_WRITE;  
			
	BURST_WRITE: begin					//STATE	10
		if(Burst_cnt==(BL-'d3))
			STATE<=BT_W;
		else
			STATE<=BURST_WRITE;
		Burst_cnt <= Burst_cnt + 1'b1;
		end  
		
	BT_W:	begin          				//STATE	11
		if(cmdack)
			STATE<=WAIT_ACK_W_T;
		else
			STATE<=BT_W;
		end

	WAIT_ACK_W_T:						//STATE	12
		STATE<=CLOSE_PAGE_W;
       
//------------------------CLOSE PAGE WRITE BURST----------------------------------	                       
	CLOSE_PAGE_W:begin					//STATE	17
		if(cmdack)
			STATE<=REFRESH_W;
		else
			STATE<=CLOSE_PAGE_W;
		end
	
	REFRESH_W: begin					//STATE	18
		if(cmdack) begin             
			STATE<=IDLE_WR;
			end
		else
			STATE<=REFRESH_W;
		end
//-------------------------------PAGE READ BURST----------------------------------	
	PAGE_READ:begin						//STATE	13
		if(cmdack)    
			STATE<=BURST_READ;
		else 
			STATE		<=	PAGE_READ;
			Burst_cnt	<=	8'b0;
			RCDCL_CNT	<=	2'b0;
      	end
	                
	BURST_READ:begin					//STATE	14
		if(Burst_cnt==('d6))
			s_enable <= 1'b1; 
		else if(Burst_cnt==(BL-3))
			STATE<=BT;
		else
			STATE<=BURST_READ;
		Burst_cnt	<=	Burst_cnt + 1'b1;
		end
		
	BT:									//STATE	15
		if(cmdack)
			STATE<=LAST_DATA;                       
		else
			STATE<=BT;                            
	
	LAST_DATA:							//STATE	16
		STATE<=CLOSE_PAGE_R;
//-------------------------CLOSE PAGE READ BURST----------------------------------	

	CLOSE_PAGE_R:begin					//STATE	19
		if(cmdack)
			STATE<=REFRESH_R;
		else
			STATE<=CLOSE_PAGE_R;
		
		if(RCDCL_CNT=='d2)
			s_enable <= 1'b0;
		else
			RCDCL_CNT <= RCDCL_CNT + 1'b1;	
		end
		
	REFRESH_R:							//STATE	20
		if(cmdack)             
			STATE<=IDLE_WR;
		else
			STATE<=REFRESH_R;
//-------------------------------------------------------------------------
	default:							//STATE	0
		STATE<=IDLE;

	endcase
end
//-----------------------------------------------------------------------
//generate the addr to the sdr_sdram_controller
always @ (STATE or w_page or r_page or r_ba or w_ba)
case(STATE)
	PRECHARGE:		addr = 21'h1f0000;
	LOAD_MR:		addr = 21'h37;//..._000_00_011_0111
	LOAD_R2:		addr = 21'h271;
	LOAD_R1:		addr = 21'h12F;
	PAGE_WRITE:		addr = {w_ba,w_page,8'b0};
	PAGE_READ:		addr = {r_ba,r_page,8'b0};
	BT_W:			addr = {w_ba,19'b0};    
	CLOSE_PAGE_W:	addr = {w_ba,19'b0};
	CLOSE_PAGE_R:	addr = {r_ba,19'b0};
	BT:				addr = {r_ba,19'b0};
	default:		addr = 21'h0;
endcase
//--------------------------------------------------------------------------
always @ (posedge clk or negedge rst)
	if(!rst)
		interrupt <= 1'b1;
	else if(wrusedw > 'd892)
		interrupt <= 1'b0;
	else
		interrupt <= 1'b1;
//---------------------------------------------------------------------------
always @ (posedge clk or negedge rst)
	if(!rst)
		s_req <= 1'b0;
	else if	(wrusedw > 'd892)
		s_req <= 1'b0;
	else if(!r_req)
		s_req <= 1'b1;
	else
		s_req <= 1'b0;
//----------------------------------------------------------------------------
always @ (posedge clk or negedge rst)
if(!rst)
	s_fifo_rst <= 0;
else if((r_page == 'd0) && STATE[13])
	s_fifo_rst <= 1;
else
	s_fifo_rst <= 0; 
//-----------------------------------------------------------------------------
	
endmodule