othertestbench.v

verilog语言写的8位CPU源代码

`timescale 1ns/10ps
module OtherTestbch;
    wire[7:0] data;
    wire [7:0] address_out;
    wire CS;
    wire READ;
    wire WRITE;
    reg clk;
    reg reset;
    
    KD_CPU b(.data(data),.address_out(address_out),.CS(CS),.READ(READ),.WRITE(WRITE),.clk(clk),.reset(reset));
    memory m(.mem_data(data),.mem_address(address_out),.CS(CS),.WRITE(WRITE),.READ(READ));
             
    initial
    begin  
    clk = 'b0;
    reset = 'b0;
    
    m.mem[0]='b0;           //mov mi -> AC
    m.mem[1]=30;            //Adress is 20     
    m.mem[2]='b00010001;    //mov AC to GR1
    
    m.mem[3]='b0;           //mov mi -> AC
    m.mem[4]=31;            //Adress is 21      
    
    m.mem[5]='b00101001;    //AC-GR->AC
    m.mem[6]=01100000;     //jmp
    m.mem[7]=107;    //jmp adress
    

    m.mem[107]='b00001000;    //mov ac to mem
    m.mem[108]='h40;
    
    m.mem[109]='b01101000;    //jNZ
    m.mem[110]=10;          //
    
    
    m.mem[10]='b0;          //mov mi->AC
    m.mem[11]=32;           //adress
    m.mem[12]=01000000;      //AC and GR
        
    m.mem[13]='b00001000;    //mov ac to mem
    m.mem[14]='h41;          //mem address is 'h41
    
    m.mem[15]='b0;          //mov mi ->AC
    m.mem[16]=33;           //address is 23
    
    m.mem[17]='b01000001;   //xor AC GR
    m.mem[18]='b00001000;    //mov ac to mem
    m.mem[19]='h42;          //mem address is 'h42
    
    m.mem[20]='b11111000;   //HLT;
    
       
    m.mem[30]='h31;
    m.mem[31]='h43;   //01000011
    m.mem[32]='h51;
    m.mem[33]='hF1;   //11110001
    
    //m.mem['h40]='h43-'h31
    //m.mem['h41]=AC and GR1
   
   #1 reset=1;
   #5000 $display( "Result is:%h.\n",m.mem[40]);
   # 5000 $stop;
   end

   always #100 clk=~clk;
 endmodule