jntestbench.v

verilog语言写的8位CPU源代码

`timescale 1ns/10ps
module JNZbench;
    wire[7:0] data;
    wire [7:0] address_out;
    wire CS;
    wire READ;
    wire WRITE;
    reg clk;
    reg reset;
    KD_CPU b(.data(data),.address_out(address_out),.CS(CS),.READ(READ),.WRITE(WRITE),.clk(clk),.reset(reset));
    memory m(.mem_data(data),.mem_address(address_out),.CS(CS),.WRITE(WRITE),.READ(READ));
             
    initial
    begin  
    clk = 'b0;
    reset = 'b0;

    ///////////////////////////////////////
    m.mem[0]='b0;//mov mi to AC
    m.mem[1]=20;
    m.mem[2]='b00010000;//AC->GR
    m.mem[3]='b01011000;//SHL
    m.mem[4]='b01110000;//jNC  
    m.mem[5]=100;
    
    m.mem[100]='b00010001;//mov AC to R1
    m.mem[101]='b0;//mov r1 to AC
    m.mem[102]=23;  
    m.mem[103]='b10010001;//AC*R1
    
    m.mem[104]='b10101000;  //mov ZYGR0 to ac
    m.mem[105]='b00001000;  //mov ac to mem
    m.mem[106]=40;          //mem address is 41
    
    m.mem[107]='b10101001;  //mov ZYGR1 to ac
    m.mem[108]='b00001000;  //mov ac to mem
    m.mem[109]=41;          //mem address is 41
    m.mem[110]='b11111000;  //HALT
    
    m.mem[20]='hF2;
    m.mem[23]='hF1;
////////////////////////////////////////////////  
   #1 reset=1;
   #7000 $display( "High is:%b,,,low is:%b\n",m.mem[40],m.mem[41]);
   # 10000 $stop;
   end

   always #100 clk=~clk;
   endmodule