zygr.v

verilog语言写的8位CPU源代码

//  module name :GR
//  discription :yi ge ji cun qi ,you jia zai he bao chi de gong neng ,rest==0   
//               wei yi bu fu wei xin hao ,c     
       
module ZYGR(ZYGR_out,ZYGR_outDIV,ZYGR_in,ZYGR_inMU,ZYGR_inS,ZYGR_inY,clk,reset,ZYGR_address,
            load_enable,MUL_outenable,DIV_outenable,DIVenable);
parameter width=8;

output[width-1:0] ZYGR_out;   //send to DB
output[15:0] ZYGR_outDIV;       //send to the DIV as dividend
input[width-1:0] ZYGR_in;     //inport of DB
input[15:0] ZYGR_inMU;         //Mu_result
input[15:0] ZYGR_inS;         //Div_result
input[7:0] ZYGR_inY;          //residue
input[2:0] ZYGR_address;      //address
input clk;
input reset;
input load_enable;
input MUL_outenable;          //Mu_result port shi neng
input DIV_outenable;
input DIVenable;              //Div_result port shi neng


reg [width-1:0] ZYGR_out;
reg [15:0] ZYGR_outDIV;  
reg [width-1:0] register[7:0];

always @( posedge clk or negedge reset )
begin
   if(!reset)
   begin
      register[0]<='b0;
      register[1]<='b0;
      register[2]<='b0;
      register[3]<='b0;
      register[4]<='b0;
      register[5]<='b0;
      register[6]<='b0;
      register[7]<='b0;
   end
               
   else
   begin  
     if(load_enable)
        begin
           if(MUL_outenable)
           begin
              register[0]<=ZYGR_inMU[15:8]; 
              register[1]<=ZYGR_inMU[7:0]; 
           end 
           else if(DIV_outenable)
                begin
                   register[2]<=ZYGR_inS[15:8]; 
                   register[3]<=ZYGR_inS[7:0];
                   register[4]<=ZYGR_inY;
                end
                else       
                begin
                   case(ZYGR_address)
                   'b000:register[0]<=ZYGR_in;
                   'b001:register[1]<=ZYGR_in;
                   'b010:register[2]<=ZYGR_in;
                   'b011:register[3]<=ZYGR_in;
                   'b100:register[4]<=ZYGR_in;
                   'b101:register[5]<=ZYGR_in;
                   'b110:register[6]<=ZYGR_in;
                   'b111:register[7]<=ZYGR_in;
                   endcase
                end
        end
   end
end

always @ (ZYGR_address or register[0] or register[1]or register[2]or register[3]
             or register[4]or register[5]or register[6]or register[7] or DIVenable)  /////////////lfd
             begin
                if(!DIVenable)
                begin
                   ZYGR_outDIV<='b0;
                   case(ZYGR_address)
                   'b000:ZYGR_out<=register[0];
                   'b001:ZYGR_out<=register[1];
                   'b010:ZYGR_out<=register[2];
                   'b011:ZYGR_out<=register[3];
                   'b100:ZYGR_out<=register[4];
                   'b101:ZYGR_out<=register[5];
                   'b110:ZYGR_out<=register[6];
                   'b111:ZYGR_out<=register[7];
                   endcase
                end
                else  
                begin 
                   ZYGR_outDIV<={register[5],register[6]};
                   ZYGR_out<='b0;
                end
            end
 
   
endmodule