multestbench.v

verilog语言写的8位CPU源代码

`timescale 1ns/10ps
module MULTITestbench;
    wire[7:0] data;
    wire [7:0] address_out;
    wire CS;
    wire READ;
    wire WRITE;
    reg clk;
    reg reset;
    
    KD_CPU b(.data(data),.address_out(address_out),.CS(CS),.READ(READ),.WRITE(WRITE),.clk(clk),.reset(reset));
    memory m(.mem_data(data),.mem_address(address_out),.CS(CS),.WRITE(WRITE),.READ(READ));
             
    initial
    begin  
    clk = 'b0;
    reset = 'b0;
    
    m.mem[0]='b0;//mov mi -> AC
    m.mem[1]=20;//Adress is 20 
    m.mem[2]='b00010001;//mov AC to GR1
    m.mem[3]='b0;//mov mi -> AC
    m.mem[4]=21;//Adress is 21  
    
    m.mem[5]='b10010001;//chengfa
     
    m.mem[6]='b10101000;//mov ZYGR0 to ac
    m.mem[7]='b00001000;//mov ac to mem
    m.mem[8]='h40;//mem address is 40
    
    m.mem[9]='b10101001;//mov ZYGR1 to ac
    m.mem[10]='b00001000;//mov ac to mem
    m.mem[11]='h41;//mem address is 41
    m.mem[12]='b11111000;//HALT
       
    m.mem[20]='h31;
    m.mem[21]='h41;  
   #1 reset=1;
   #5000 $display( "Result is:%h.\n",m.mem[40]);
   # 5000 $stop;
   end

   always #100 clk=~clk;
 endmodule