multi.v

verilog语言写的8位CPU源代码

`timescale 1ns/10ps
module mulit(result,op_a,op_b,MUE);

input [7:0] op_a,op_b;
input MUE;
output [15:0]result;
reg [15:0] result;
reg[7:0] shift_opb,shift_opa;
always@(op_a or op_b or MUE)
	begin
		result=0;
		shift_opa=op_a;
		shift_opb=op_b;
		if(MUE=='b1)
			begin 
			if(shift_opb[0]) result[8:0]=result[8:0]+shift_opa ;
			if(shift_opb[1]) result[9:1]=result[9:1]+shift_opa;
			if(shift_opb[2]) result[10:2]=result[10:2]+shift_opa;
			if(shift_opb[3]) result[11:3]=result[11:3]+shift_opa;
			if(shift_opb[4]) result[12:4]=result[12:4]+shift_opa;
			if(shift_opb[5]) result[13:5]=result[13:5]+shift_opa;
			if(shift_opb[6]) result[14:6]=result[14:6]+shift_opa;
			if(shift_opb[7]) result[15:7]=result[15:7]+shift_opa;

		end
		else result=0;
	end
endmodule