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gb-v
%!PS-Adobe-3.0 Resource-CMap
%%DocumentNeededResources: ProcSet (CIDInit)
%%DocumentNeededResources: CMap (GB-H)
%%IncludeResource: ProcSet (CIDInit)
%%IncludeResource: CMap (GB-H)
%%BeginResourc
gbt-v
%!PS-Adobe-3.0 Resource-CMap
%%DocumentNeededResources: ProcSet (CIDInit)
%%DocumentNeededResources: CMap (GBT-H)
%%IncludeResource: ProcSet (CIDInit)
%%IncludeResource: CMap (GBT-H)
%%BeginResou
train.v
// Example Verilog State machine to control trains File: Tcontrol.v
module train (reset, clock, sensor1, sensor2, sensor3, sensor4, sensor5,
switch1, switch2, switch3, dirA, dirB,CLOCK_50);
top.v
`timescale 1ns/10ps
module top;
reg clk=0;
always #10 clk=~clk;
integer seed1=1,seed2=2,seed3=3,seed4=4,
seed5=5,seed6=6,seed7=7,seed8=8;
reg [3:0] a1,a2,a3,a4,a5,a6,a7,a8;
wire [7
mul.v
`timescale 1ns/10ps
module mul(//input
clk,nrst,
a,b,mul_en,
//output
oen,product);
in
top.v
`timescale 1ns/10ps
module top;
reg clk=0,nrst=0,mul_en=0;
reg [15:0] temp;
wire [15:0] product;
wire oen;
always #20 clk=~clk;
initial
begin
#41 nrst=0;
#85 nrst=1;
#25
top.v
`timescale 1ns/10ps
module top;
parameter
row=96,
col=96,
rowsize =7,
col_size =7,
word_size = 16,
address_size = row * col,
display_size
comp.v
`timescale 1ns/10ps
`define raw_bits 0
module comp(a1,a2,min,max);
input [`raw_bits+3:0] a1,a2;
output [`raw_bits+3:0] min,max;
wire [`raw_bits+3:0] min,max;
wire a1_bigger_than_a2=(a
dff.v
module dff(clk,A,B,C);
input clk,A,B,C;
always@(posedge clk)
begin
B=A;
A=C;
end
always@(posedge clk)
begin
B