top.v

来自「精通VerilogHDL：IC设计核心技术实例详解」· Verilog 代码 · 共 79 行

`timescale 1ns/10ps

module top;
parameter
        row=96,
        col=96,        
        rowsize  =7,
        col_size =7,
        word_size = 16,
	address_size = row * col,
	display_size = row * word_size,		
	row_size = row * word_size;

reg clk=0,nrst=1,CS=0,read=0;
reg [col_size-1:0] ROW,COL,DISP_ROW=0;
always #50 clk=~clk; 
initial begin
 #150 nrst=0;
 #20  CS=1;
 #20  nrst=1;
 #1000 ;
 wait (ROW==7'd96);
 read=1;
 wait (ROW==7'd10);
 $finish;
end

wire [word_size-1:0] DO; 
reg  [word_size-1:0] din; 
always@(posedge clk or negedge nrst)
 if (~nrst) din<=0;
 else       din<=$random;
 

always@(posedge clk or negedge nrst)
 if (~nrst)           COL<=0;
 else if (COL==7'd96) COL<=0;
 else                 COL<=COL+1;
  
always@(posedge clk or negedge nrst)
 if (~nrst)           ROW<=0;
 else if (ROW==7'd96) ROW<=0;
 else if (COL==7'd96) ROW<=ROW+1;
  
wire #25 WR=(~read)?clk:0; 
wire #25 RD=( read)?clk:0; 

always@(posedge clk)
begin
 if (read)begin
  if (DISP_ROW==95) DISP_ROW<=#1 0;
  else              DISP_ROW<=#1 DISP_ROW+1;
 end                   
end  
wire #25 DISP_EN=read? clk : 0;  
wire [display_size-1:0] DISP_DO;
 
mem96x96x16 mem96x96x16(
    //MCU interface
      .CS       (CS),
      .WR       (WR),
      .RD       (RD),
      .DIN      (din),
      .ROW      (ROW),
      .COL      (COL),
      .DO       (DO),
      
    //drivewr interface                                       
      .DISP_EN  (DISP_EN),
      .DISP_ROW (DISP_ROW),
      .DISP_DO  (DISP_DO)); 

initial
begin
    $dumpfile("./debussy/mem.vcd");
    $dumpvars(0,top);          
end          

endmodule