top.v

来自「精通VerilogHDL：IC设计核心技术实例详解」· Verilog 代码 · 共 46 行

`timescale 1ns/10ps   
module top;

reg clk=0;
always #10 clk=~clk;
integer seed1=1,seed2=2,seed3=3,seed4=4,
        seed5=5,seed6=6,seed7=7,seed8=8;
reg [3:0] a1,a2,a3,a4,a5,a6,a7,a8;
wire [7:0] sum;
always@(posedge clk)
begin
  a1<=$random(seed1);
  a2<=$random(seed2);
  a3<=$random(seed3);
  a4<=$random(seed4);
  a5<=$random(seed5);
  a6<=$random(seed6);
  a7<=$random(seed7);
  a8<=$random(seed8);
end

csa8_4 csa8_4( //input
          a1,a2,a3,a4,a5,a6,a7,a8,

         //output          
          sum);  

wire err_found=(sum!=(a1+a2+a3+a4+a5+a6+a7+a8));        

always@(negedge clk)
begin
 if (err_found)begin
   $display("time: %t",$time);
   $display("error happen at a1=%d a2=%d a3=%d a4=%d",a1,a2,a3,a4);
   $display("error happen at a5=%d a6=%d a7=%d a8=%d",a5,a6,a7,a8);
   $display("exact:%5d but got%d",(a1+a2+a3+a4+a5+a6+a7+a8),sum);
   #200000 $stop;
 end  
end
 
initial
begin
  $dumpfile("./csa.vcd");    
  $dumpvars(0,top);          
end
endmodule