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regfile.v
// ARM 7 Register File
// Jeffrey J. Cook
// ** UNTESTED, BEWARE **
`timescale 1ns/100ps
`define ADDRLEN 4
`define DBUSLEN 32
`define FLAGSLEN 11
`define CPSRSEL 0
`define SPSRSEL 1
`define MODE_
booth.v
//Name: Tam N. Nguyen, Thinh le, & Long Pham
//Behave of Booth Multiplier.
`define MULT_NUM_STATE_BITS 2
`define MULT_IDLE 2'b00
`define MULT_SHIFT 2'b01
`define MULT_RESULT 2'b10
`timescale
armdatapath.v
// ARM Datapath Module
// Instantiates all other modules, to be used with ARM Controller
// Deanna Perry
// 4/3/00
// Updated by Matt Crum on 4/6/00 -- cleaned up parameter list and wire
//
armcontroller.v
//////////////////////////////////////////////////
// //
// ARM Controller Mixed Model //
// Revision History
defines.v
// defines.v
// States in the ARM
`define NUM_STATE_BITS 6
`define INIT 6'b000000
`define F1 6'b000001
`define RESET 6'b000010
`define ABORT_DATA 6'b000011
`define ABORT_PREFETCH 6'b000100
`def
supercpsr.v
// To specify a specific mode, set SC_CTRL_Type = 10000 and SC_CTRL_Source to the mode you want
// See the defines file to see the available mode definitions, are in the form SC_CTRL_SELECT_SOURCE_XXX
barrel.v
// Barrel Shifter with 32 bit input & 32 bit output
`timescale 1ns/100ps
module Barrel_Shifter(BS_Enable,BS_Input_Bus,BS_Shift_Type,BS_Shift_Amt,BS_Cin,BS_Shift_Output,BS_Cout);
input[31:0] BS_Inpu
dct.v
//dct.v
module dct( clk, rst_b, d_rdy, start, d_in,
calc_done, d_en, d_out, w1_done, w2_done);
input clk, rst_b, d_rdy;
wire clk, rst_b, d_rdy;
input [1:0]start;
alu.v
//Name: Tam Nguyen, Long Pham, Thinh Le
//Behavior of ALU:
//Last modified 4/30/00
//`include "/work1/ece371emr/mcrum/.archCVS/defines.v"
`include "defines.v"
`timescale 1ns/100ps
module ALU_ARM7(A