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// Memory Interface - Main ASM. `timescale 1ns/100ps module CPU_coupler(D, A, nMREQ, nRW, MAS, nWAIT, sysclk, reset, Store_Trigger, Load_Trigger, write_buffer_data, write_buffer_addr, write_b

// SDRAM model with AVL implementation source file. // written by Chris Fester 4-5-00 `timescale 1ns/100ps module SDRAM_model_AVL(Addr, Data, nRAS, nCAS, nWE, SEQ, nCS, MCLK, BYTE); input [31:0

// Top level source file for the Memory Interface `define BEHAVIORAL 1 `timescale 1ns/100ps `include "Memoryside.v" `include "CPUside.v" //`include "AVLMemory.v" `include "SimpleMemory.v" module M

`define TIME_LIMIT 110000 module c1(clk); output clk; reg clk; always begin if ($time == 0) begin clk = 0; end #50 clk = ~

// miscellaneous devices for ARM7 Controller Datapath // Deanna Perry, 4/3/00 // mux2, mux24, mux4, mux44, mux8, mux84, decoder, add4, clearable_register // mux2 // 2 32-bit input multiplexor

// SDRAM model (simple) source file // written by Chris Fester 4-2-00 `timescale 1ns/100ps // define a 32K size memory address bit range // `define MEM_WORDS 8192 // `define MEM_ADDR_BITS 13 `defin

// Verilog source file for the MemoryASM // Written by Chris Fester 3-28-00 // This represents the "memory controller" side of the Memory Interface. It runs // with the assumption that it is being co

// ARM 7 Register File // Jeffrey J. Cook // ** UNTESTED, BEWARE ** `timescale 1ns/100ps `define ADDRLEN 4 `define DBUSLEN 32 `define FLAGSLEN 11 `define CPSRSEL 0 `define SPSRSEL 1 `define MODE_

//Name: Tam N. Nguyen, Thinh le, & Long Pham //Behave of Booth Multiplier. `define MULT_NUM_STATE_BITS 2 `define MULT_IDLE 2'b00 `define MULT_SHIFT 2'b01 `define MULT_RESULT 2'b10 `timescale

// ARM Datapath Module // Instantiates all other modules, to be used with ARM Controller // Deanna Perry // 4/3/00 // Updated by Matt Crum on 4/6/00 -- cleaned up parameter list and wire //