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V 的代码
armcontroller.v
//////////////////////////////////////////////////
// //
// ARM Controller Mixed Model //
// Revision History
defines.v
// defines.v
// States in the ARM
`define NUM_STATE_BITS 6
`define INIT 6'b000000
`define F1 6'b000001
`define RESET 6'b000010
`define ABORT_DATA 6'b000011
`define ABORT_PREFETCH 6'b000100
`def
supercpsr.v
// To specify a specific mode, set SC_CTRL_Type = 10000 and SC_CTRL_Source to the mode you want
// See the defines file to see the available mode definitions, are in the form SC_CTRL_SELECT_SOURCE_XXX
barrel.v
// Barrel Shifter with 32 bit input & 32 bit output
`timescale 1ns/100ps
module Barrel_Shifter(BS_Enable,BS_Input_Bus,BS_Shift_Type,BS_Shift_Amt,BS_Cin,BS_Shift_Output,BS_Cout);
input[31:0] BS_Inpu
alu.v
//Name: Tam Nguyen, Long Pham, Thinh Le
//Behavior of ALU:
//Last modified 4/30/00
//`include "/work1/ece371emr/mcrum/.archCVS/defines.v"
`include "defines.v"
`timescale 1ns/100ps
module ALU_ARM7(A
cpuside.v
// Memory Interface - Main ASM.
`timescale 1ns/100ps
module CPU_coupler(D, A, nMREQ, nRW, MAS, nWAIT, sysclk, reset, Store_Trigger, Load_Trigger,
write_buffer_data, write_buffer_addr, write_b
avlmemory.v
// SDRAM model with AVL implementation source file.
// written by Chris Fester 4-5-00
`timescale 1ns/100ps
module SDRAM_model_AVL(Addr, Data, nRAS, nCAS, nWE, SEQ, nCS, MCLK, BYTE);
input [31:0
memoryinterface.v
// Top level source file for the Memory Interface
`define BEHAVIORAL 1
`timescale 1ns/100ps
`include "Memoryside.v"
`include "CPUside.v"
//`include "AVLMemory.v"
`include "SimpleMemory.v"
module M
clock.v
`define TIME_LIMIT 110000
module c1(clk);
output clk;
reg clk;
always
begin
if ($time == 0)
begin
clk = 0;
end
#50 clk = ~
accessories.v
// miscellaneous devices for ARM7 Controller Datapath
// Deanna Perry, 4/3/00
// mux2, mux24, mux4, mux44, mux8, mux84, decoder, add4, clearable_register
// mux2
// 2 32-bit input multiplexor
// Inp