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// SDRAM model (simple) source file // written by Chris Fester 4-2-00 `timescale 1ns/100ps // define a 32K size memory address bit range // `define MEM_WORDS 8192 // `define MEM_ADDR_BITS 13 `defin

// Verilog source file for the MemoryASM // Written by Chris Fester 3-28-00 // This represents the "memory controller" side of the Memory Interface. It runs // with the assumption that it is being co

module ctrl_eth ( wb_clk_i,wb_rst_i, wb_adr_o,wb_dat_i,wb_dat_o, wb_sel_o,wb_we_o, wb_stb_o,wb_cyc_o, wb_ack_i,led ); input wb_clk_i; input wb_rst_i; input wb_ack_i

`define CYCLONE `define CLK_DIV 1 `define ETH_eth `define SPI `define APP_ADDR_DEC_W 8 `define APP_ADDR_SRAM `APP_ADDR_DEC_W'h00 `define APP_ADDR_SD `APP_ADDR_DEC_W'h92

`timescale 1ns /100ps

////////////////////////////////////////////////////////////////////// //// //// //// readWriteSDBlock.v ////

////////////////////////////////////////////////////////////////////// //// //// //// spiCtrl.v

////////////////////////////////////////////////////////////////////// //// //// //// spiTxRxData.v

////////////////////////////////////////////////////////////////////// // timescale.v ////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////// //// //// //// sendCmd.v