代码搜索结果
找到约 10,000 项符合
V 的代码
serial.v
/*
本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。
程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位，8个数据位，1个结束位。
串口的波特律由程序中定义的di<mark>v</mark>_par参数决定，更改该参数可以实现相应的波特率。程序当前设定的di<mark>v</mark>_par 的值
是0x145，对应的波特率是9600。用 ...
ledwater.v
/*跑马灯实验：利用计数器轮流点亮LED灯，实现各种动态效果。
*/
module ledwater(clk,rst,dataout);
input clk,rst;
output[7:0] dataout;
reg[7:0] dataout;
reg[22:0] cnt;
always@(posedge clk or negedge rst)
begin
if
pic.v
//
// SYNTHETIC PIC 2.0 4/23/98
//
// This is a synthesizable Microchip 16C57 compatible
// microcontroller. This core is not intended as a high fi
shifter.v
module shifter(in,clock,reset,out);
input in,clock,reset;
output [7:0] out;
reg [7:0] out;
always@(posedge clock)
begin
if(reset)
out=8'b0000;
else
test.v
//////////////////////////////////////////////////////////////
////////Module name :test /////////////
////////Function :used to test
all.v
module all (a,b,y);
input [7:0] a,b;
output [8:0] y;
function [8:0] add_It_10;
input [7:0] a,b;
reg [7:0] temp;
begin
if(b
onehot.v
//
// Just a little demo of some FSM techniques, including One-Hot and
// using 'default' settings and the case statements to selectively
// update registers (sort of like J-K flip-flops).
//
//
dds.v
//
//
// This is just a little demo of DDS. It doesn't have any cool features
// or anything..
//
module dds (
clk,
reset,
din,
dout
);
parameter W = 12;
input
framer.v
//
// Simple example of a "framer". In this case, an MPEG framer where
// data is sent in 188-byte frames which begin with a special SYNC character
// defined as 47 hex. Framing must, of course,
fifo.v
// Synchronous FIFO. 4 x 16 bit words.
//
module fifo (clk, rstp, din, writep, readp, dout, emptyp, fullp);
input clk;
input rstp;
input [15:0] din;
input readp;
input writep;
output [15: