代码搜索结果

`include "defs.h" module backtrack(cmp, restart, clk, bit_line); input [16-1:0] cmp; input restart, clk; output [1:0] bit_line; wire out000, out001, out010, out011, out

`include "defs.h" module decoder(encoded_signal, bit_line, reset, clk); input [16-1:0] encoded_signal; input reset; output [3:0] bit_line; input clk; wire [`S-1:0] sum_enc_bits0, sub

`include "defs.h" module block(sum_enc_bits0, sub_enc_bits0, sum_enc_bits1, sub_enc_bits1, cmp, reset, clk); input reset, clk; input [4-1:0] sum_enc_bits0, sub_enc_bits0, sum_enc_bits1,

`include "defs.h" module input_signal(out, reset, clk); output [16-1:0]out; input reset, clk; reg [`S-1:0] enc_bit01, enc_bit02, enc_bit11, enc_bit12; assign out = {enc_bit01, enc_bit02, enc_bi

`include "defs.h" module stage(in00, in01, in10, in11, in20, in21, in30, in31, sum_enc_bits, sub_enc_bits, out00, out01, out10, out11, out20, out21, out30, out31, cmp); i

@(negedge reset) enc_bit01 = -4; enc_bit02 = -4; enc_bit11 = -4; enc_bit12 = 3; @(posedge clk) enc_bit01 = 3; enc_bit02 = 3; enc_bit11 = 3; enc_bit12 = -4; @(posedge clk) enc_b

`include "defs.h" module backtrack(cmp, restart, clk, bit_line); input [16-1:0] cmp; input restart, clk; output [3:0] bit_line; wire out000, out001, out010, out011, out020, out

`include "defs.h" module decoder(encoded_signal, bit_line, reset, clk); input [48-1:0] encoded_signal; input reset; output [11:0] bit_line; input clk; wire [`S-1:0] sum_enc_bits0,

`include "defs.h" module block(sum_enc_bits0, sub_enc_bits0, sum_enc_bits1, sub_enc_bits1, sum_enc_bits2, sub_enc_bits2, sum_enc_bits3, sub_enc_bits3, sum_enc_bits4, sub_enc_

`include "defs.h" module input_signal(out, reset, clk); output [48-1:0]out; input reset, clk; reg [`S-1:0] enc_bit01, enc_bit02, enc_bit11, enc_bit12, enc_bit21, enc_bit22, enc_bit31,