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lwbsram.v
/////////////////////////////////////////////////////////////////////
//// ////
//// LWB rev 1.2 -- SRAM INTERFACE
lwbdecode.v
/////////////////////////////////////////////////////////////////////
//// ////
//// LWB rev 1.2 -- Memory Address Decode
isa.v
module isa(sa,sd,bclk,aen,bale,io16,iorc,iowc,iochkrdy ,drq1,dack1);
parameter io_reg0_addr='h300;
parameter io_reg1_addr='h302;
input aen;
input [11:0] sa;
inout [15:0] sd;
input bclk;
inp
timescale.v
`timescale 1ns/10ps
cosfunc.v
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation,
costest.v
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation,
multiplier.v
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation,
timescale.v
`timescale 1ns / 10ps
timescale.v
`timescale 1ns / 10ps
lfsr.v
/////////////////////////////////////////////////////////////////////
//// ////
//// Linear Feedback Shift Register