代码搜索结果
找到约 10,000 项符合
V 的代码
set.v
// Copyright Model Technology, a Mentor Graphics
// Corporation company 2003, - All rights reserved.
`timescale 1ns/1ns
module cache_set(addr, data, hit, oen, wen);
input addr, oen, wen;
inout
memory.v
// Copyright Model Technology, a Mentor Graphics
// Corporation company 2003, - All rights reserved.
`timescale 1 ns / 1 ns
module memory(clk, addr, data, rw, strb, rdy);
input clk, addr, rw, s
gates.v
// Copyright Model Technology, a Mentor Graphics
// Corporation company 2003, - All rights reserved.
`timescale 1 ns / 1 ns
///////////////////////////////////////////////////
// and2 cell:
// W
top.v
// Copyright Model Technology, a Mentor Graphics
// Corporation company 2003, - All rights reserved.
`timescale 1 ns / 1 ns
module top;
reg clk;
// Processor bus signals
wire prw, pstrb, prdy
proc.v
// Copyright Model Technology, a Mentor Graphics
// Corporation company 2003, - All rights reserved.
`timescale 1 ns / 1 ns
module proc(clk, addr, data, rw, strb, rdy);
input clk, rdy;
outp
cache.v
// Copyright Model Technology, a Mentor Graphics
// Corporation company 2003, - All rights reserved.
`timescale 1 ns / 1 ns
module cache(clk, paddr, pdata, prw, pstrb, prdy,
saddr,
timescale.v
`timescale 1ns/10ps
song.v
//*******************************this work is awarded by YangXiao and TangXiaobin********
//******************************* version : 2 ********
//***************
fifosel.v
module FIFOSEL(addr,fifosel,ecs);
input[11:0] addr;
input ecs;
output fifosel;
wire tempa;
assign fifosel=((~ecs)&tempa);
assign tempa=(addr[11:5]==7'b1000000)?1'b1:1'b0;
endmodule
spiprocess.v
module spiprocess(clk,cpurd,cpuwr,cpusel,cpuindata,ramindata,outdata,addr,mosi,miso,reset,irq,CSN,SCK,RFirq,SendAddr,SendRDen,ReceiveData,ReceiveAddr,SendramCLK,ReceiveCLK,ReceiveWen,CE,sendfinishtest