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decode.v
module decode (binary,one_hot);
input [3:0] binary;
output[9:0] one_hot;
reg [9:0] one_hot;
always @(binary)
begin
case (binary)
4'b0001 : one_hot = 10'b0000000001; //1
4'b0010 : on
tenths.v
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation,
decode.v
module decode (binary,one_hot);
input [3:0] binary;
output[9:0] one_hot;
reg [9:0] one_hot;
always @(binary)
begin
case (binary)
4'b0001 : one_hot = 10'b0000000001; //1
4'b0010 : on
tenths.v
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation,
tenths.v
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation,
tenths.v
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation,
top.v
module top (ipad_dll_clk_in, dll_rst, top2a_c, top2b, obuft_out,
mod_c_out, moda_data, moda_clk_pad, moda_out, modb_data,
modb_clk_pad, modb_out, modc_data, modc_clk_pad, modc_out) ;
inp
module_a.v
module module_a ( CLK_TOP, B2A_IN, TOP2A_IN, C2A_IN, MODA_DATA,
MODA_CLK, MODA_OUT, A2B_OUT, A2TOP_OBUFT_I_OUT, A2C_OUT);
input CLK_TOP ;
input B2A_IN ;
input TOP2A_IN ;
input C2A_IN ;
top.v
// Xilinx Verilog produced by program ngd2ver F.28
// Command: top.nga
// Input file: top.nga
// Output file: top.v
// Design name: top
// Xilinx: J:/eda/Xilinx
// # of Entities: 1
// Device: 2v40cs1
module_a.v
module module_a ( CLK_TOP, B2A_IN, TOP2A_IN, C2A_IN, MODA_DATA,
MODA_CLK, MODA_OUT, A2B_OUT, A2TOP_OBUFT_I_OUT, A2C_OUT);
input CLK_TOP ;
input B2A_IN ;
input TOP2A_IN ;
input C2A_IN ;