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V 的代码
timescale.v
`timescale 1ns / 10ps
fpgasong.v
module song(clk_6MHz,clk_4Hz,speaker,high,med,low);
input clk_6MHz, clk_4Hz;
output speaker;
output[3:0] high,med,low;
reg[3:0] high,med,low;
reg[13:0] divider,origin;
reg[7:0] counter;
reg spe
wram.v
// WARNING: Do NOT edit the input and output ports in this file in a text
// editor if you plan to continue editing the block that represents it in
// the Block Editor! File corruption is VERY likel
pan.v
//megafunction wizard: %Altera SOPC Builder%
//GENERATION: STANDARD
//VERSION: WM1.0
mydram.v
// WARNING: Do NOT edit the input and output ports in this file in a text
// editor if you plan to continue editing the block that represents it in
// the Block Editor! File corruption is VERY likel
testmyfifo.v
`include "myfifo.vo"
`timescale 1ns/1ns
module t;
reg we,wr_clk,rd_clk;
reg [3:0] page;
reg [13:0] data;
reg [6:0] wr_addr,rd_addr;
wire [16:0] d;
reg [7:0] step;
initial
begin
we=1;
watchdog.v
// WARNING: Do NOT edit the input and output ports in this file in a text
// editor if you plan to continue editing the block that represents it in
// the Block Editor! File corruption is VERY likel
ram.v
// WARNING: Do NOT edit the input and output ports in this file in a text
// editor if you plan to continue editing the block that represents it in
// the Block Editor! File corruption is VERY likel
myram.v
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_ram_dq
// ============================================================
// File Name: myram.v
//
countled.v
module countled(k,a);
input k;
output a;
reg [2:0] a;
//reg [7:0] count;
always @(posedge k)
begin
if(a>=6)
begin
a=0;
end
else
a=a+1;
end
e