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V 的代码
timescale.v
`timescale 1ns / 10ps
timescale.v
`timescale 1ns / 10ps
lwbbuschange.v
/////////////////////////////////////////////////////////////////////
//// ////
//// LWB rev 1.2 -- BUS CHANGE FOR TWO SRAMS
lwbsram.v
/////////////////////////////////////////////////////////////////////
//// ////
//// LWB rev 1.2 -- SRAM INTERFACE
lwbdecode.v
/////////////////////////////////////////////////////////////////////
//// ////
//// LWB rev 1.2 -- Memory Address Decode
decoder.v
`include "defs.h"
module decoder(encoded_signal, bit_line, reset, clk);
input [8-1:0] encoded_signal;
input reset;
output [1:0] bit_line;
input clk;
wire [`S-1:0] sum_enc_bits0,
block.v
`include "defs.h"
module block(sum_enc_bits0, sub_enc_bits0, cmp, reset, clk);
input reset, clk;
input [4-1:0] sum_enc_bits0, sub_enc_bits0;
output [8-1:0] cmp;
wire [`W-1:0]
top.v
`include "defs.h"
module input_signal(out, reset, clk);
output [8-1:0]out;
input reset, clk;
reg [`S-1:0] enc_bit01, enc_bit02;
assign out = {enc_bit01, enc_bit02};
initial
begin
`inclu
stage.v
`include "defs.h"
module stage(in00, in01, in10, in11, in20, in21, in30, in31, in40,
in41, in50, in51, in60, in61, in70, in71,
sum_enc_bits, sub_enc_bits,
in_signal.v
@(negedge reset)
enc_bit01 = -4;
enc_bit02 = -4;
@(posedge clk)
enc_bit01 = -4;
enc_bit02 = -4;
@(posedge clk)
enc_bit01 = 3;
enc_bit02 = 3;
@(posedge clk)
enc_bit01 = -4;
enc_b