stage.v

viterbi译码器的一种fpga实现

`include "defs.h"

module stage(in00,  in01,  in10,  in11,  in20,  in21,  in30,  in31,  in40, 
 in41,  in50,  in51,  in60,  in61,  in70,  in71,  
             sum_enc_bits,  sub_enc_bits,  
             out00,  out01,  out10,  out11,  out20,  out21,  out30,  out31, 
 out40,  out41,  out50,  out51,  out60,  out61,  out70,  out71,  cmp);

input    [8-1:0] in00,  in01,  in10,  in11,  in20,  in21,  in30,  in31, 
 in40,  in41,  in50,  in51,  in60,  in61,  in70,  in71;
input    [4-1:0] sum_enc_bits,  sub_enc_bits;
output   [8-1:0] out00,  out01,  out10,  out11,  out20,  out21,  out30, 
 out31,  out40,  out41,  out50,  out51,  out60,  out61,  out70,  out71;
output   [8-1:0] cmp;

ACS1_0 state0(in00,  in01,  sum_enc_bits,   out00,  out01,  cmp[0]);
ACS2_0 state1(in10,  in11,  sub_enc_bits,   out10,  out11,  cmp[1]);
ACS1_1 state2(in20,  in21,  sum_enc_bits,   out20,  out21,  cmp[2]);
ACS2_1 state3(in30,  in31,  sub_enc_bits,   out30,  out31,  cmp[3]);
ACS1_1 state4(in40,  in41,  sum_enc_bits,   out40,  out41,  cmp[4]);
ACS2_1 state5(in50,  in51,  sub_enc_bits,   out50,  out51,  cmp[5]);
ACS1_0 state6(in60,  in61,  sum_enc_bits,   out60,  out61,  cmp[6]);
ACS2_0 state7(in70,  in71,  sub_enc_bits,   out70,  out71,  cmp[7]);

endmodule