decoder.v

viterbi译码器的一种fpga实现

`include "defs.h"

module decoder(encoded_signal,  bit_line,  reset,  clk);

input  [8-1:0] encoded_signal;
input           reset;
output [1:0]  bit_line;

input clk;

wire  [`S-1:0] sum_enc_bits0,  sub_enc_bits0;
wire  [8-1:0] cmp;
reg   [8-1:0] cmp0,  cmp1,  cmp2,  cmp3,  cmp4,  cmp5,  cmp6,  cmp7,  cmp8, 
 cmp9,  cmp10,  cmp11,  cmp12,  cmp13,  cmp14,  cmp15,  cmp16,  cmp17,  cmp18, 
 cmp19,  cmp20,  cmp21,  cmp22,  cmp23,  cmp24,  cmp25,  cmp26,  cmp27,  cmp28, 
 cmp29,  cmp30,  cmp31,  cmp32,  cmp33,  cmp34,  cmp35,  cmp36,  cmp37, 
 cmp38;
reg   [16-1:0] b_cmp0,  b_cmp1,  b_cmp2,  b_cmp3,  b_cmp4,  b_cmp5, 
 b_cmp6,  b_cmp7,  b_cmp8,  b_cmp9,  b_cmp10,  b_cmp11,  b_cmp12,  b_cmp13, 
 b_cmp14,  b_cmp15,  b_cmp16,  b_cmp17,  b_cmp18,  b_cmp19;
wire  restart;

block blk(sum_enc_bits0,  sub_enc_bits0,  cmp,  reset,  clk);

backtrack bt(b_cmp0,  restart,  clk,  bit_line);


assign sum_enc_bits0 = encoded_signal[7:4] + encoded_signal[3:0];

assign sub_enc_bits0 = encoded_signal[7:4] - encoded_signal[3:0];

always @(posedge clk) cmp38 = #5 cmp37;
always @(posedge clk) cmp37 = #5 cmp36;
always @(posedge clk) cmp36 = #5 cmp35;
always @(posedge clk) cmp35 = #5 cmp34;
always @(posedge clk) cmp34 = #5 cmp33;
always @(posedge clk) cmp33 = #5 cmp32;
always @(posedge clk) cmp32 = #5 cmp31;
always @(posedge clk) cmp31 = #5 cmp30;
always @(posedge clk) cmp30 = #5 cmp29;
always @(posedge clk) cmp29 = #5 cmp28;
always @(posedge clk) cmp28 = #5 cmp27;
always @(posedge clk) cmp27 = #5 cmp26;
always @(posedge clk) cmp26 = #5 cmp25;
always @(posedge clk) cmp25 = #5 cmp24;
always @(posedge clk) cmp24 = #5 cmp23;
always @(posedge clk) cmp23 = #5 cmp22;
always @(posedge clk) cmp22 = #5 cmp21;
always @(posedge clk) cmp21 = #5 cmp20;
always @(posedge clk) cmp20 = #5 cmp19;
always @(posedge clk) cmp19 = #5 cmp18;
always @(posedge clk) cmp18 = #5 cmp17;
always @(posedge clk) cmp17 = #5 cmp16;
always @(posedge clk) cmp16 = #5 cmp15;
always @(posedge clk) cmp15 = #5 cmp14;
always @(posedge clk) cmp14 = #5 cmp13;
always @(posedge clk) cmp13 = #5 cmp12;
always @(posedge clk) cmp12 = #5 cmp11;
always @(posedge clk) cmp11 = #5 cmp10;
always @(posedge clk) cmp10 = #5 cmp9;
always @(posedge clk) cmp9 = #5 cmp8;
always @(posedge clk) cmp8 = #5 cmp7;
always @(posedge clk) cmp7 = #5 cmp6;
always @(posedge clk) cmp6 = #5 cmp5;
always @(posedge clk) cmp5 = #5 cmp4;
always @(posedge clk) cmp4 = #5 cmp3;
always @(posedge clk) cmp3 = #5 cmp2;
always @(posedge clk) cmp2 = #5 cmp1;
always @(posedge clk) cmp1 = #5 cmp0;
always @(posedge clk) cmp0 = #5 cmp;

always @(posedge clk) b_cmp0 = #5 restart == 1 ? {cmp , 
 cmp0} : b_cmp1;
always @(posedge clk) b_cmp1 = #5 restart == 1 ? {cmp1 , 
 cmp2} : b_cmp2;
always @(posedge clk) b_cmp2 = #5 restart == 1 ? {cmp3 , 
 cmp4} : b_cmp3;
always @(posedge clk) b_cmp3 = #5 restart == 1 ? {cmp5 , 
 cmp6} : b_cmp4;
always @(posedge clk) b_cmp4 = #5 restart == 1 ? {cmp7 , 
 cmp8} : b_cmp5;
always @(posedge clk) b_cmp5 = #5 restart == 1 ? {cmp9 , 
 cmp10} : b_cmp6;
always @(posedge clk) b_cmp6 = #5 restart == 1 ? {cmp11 , 
 cmp12} : b_cmp7;
always @(posedge clk) b_cmp7 = #5 restart == 1 ? {cmp13 , 
 cmp14} : b_cmp8;
always @(posedge clk) b_cmp8 = #5 restart == 1 ? {cmp15 , 
 cmp16} : b_cmp9;
always @(posedge clk) b_cmp9 = #5 restart == 1 ? {cmp17 , 
 cmp18} : b_cmp10;
always @(posedge clk) b_cmp10 = #5 restart == 1 ? {cmp19 , 
 cmp20} : b_cmp11;
always @(posedge clk) b_cmp11 = #5 restart == 1 ? {cmp21 , 
 cmp22} : b_cmp12;
always @(posedge clk) b_cmp12 = #5 restart == 1 ? {cmp23 , 
 cmp24} : b_cmp13;
always @(posedge clk) b_cmp13 = #5 restart == 1 ? {cmp25 , 
 cmp26} : b_cmp14;
always @(posedge clk) b_cmp14 = #5 restart == 1 ? {cmp27 , 
 cmp28} : b_cmp15;
always @(posedge clk) b_cmp15 = #5 restart == 1 ? {cmp29 , 
 cmp30} : b_cmp16;
always @(posedge clk) b_cmp16 = #5 restart == 1 ? {cmp31 , 
 cmp32} : b_cmp17;
always @(posedge clk) b_cmp17 = #5 restart == 1 ? {cmp33 , 
 cmp34} : b_cmp18;
always @(posedge clk) b_cmp18 = #5 restart == 1 ? {cmp35 , 
 cmp36} : b_cmp19;
always @(posedge clk) b_cmp19 = #5 {cmp37,  cmp38};

reg [5-1:0] cnt;
assign restart = cnt == 19;
always @(posedge clk)
       if (reset == 1) cnt = 0;
       else if (cnt == 19) cnt = 0;
            else cnt = cnt + 1;

endmodule