block.v

viterbi译码器的一种fpga实现

`include "defs.h"

module block(sum_enc_bits0,  sub_enc_bits0,  cmp,  reset,  clk);

input            reset,  clk;
input   [4-1:0] sum_enc_bits0,  sub_enc_bits0;
output  [8-1:0] cmp;
wire    [`W-1:0] out000,  out001,  out010,  out011,  out020,  out021, 
 out030,  out031,  out040,  out041,  out050,  out051,  out060,  out061, 
 out070,  out071;
reg     [`W-1:0] ns000,  ns001,  ns010,  ns011,  ns020,  ns021,  ns030, 
 ns031,  ns040,  ns041,  ns050,  ns051,  ns060,  ns061,  ns070,  ns071;

stage  st0(ns000,  ns011,  ns030,  ns021,  ns050,  ns041,  ns060,  ns071, 
 ns010,  ns001,  ns020,  ns031,  ns040,  ns051,  ns070,  ns061, 
         sum_enc_bits0,  sub_enc_bits0, 
         out000,  out001,  out010,  out011,  out020,  out021,  out030, 
 out031,  out040,  out041,  out050,  out051,  out060,  out061,  out070, 
 out071,  cmp[7:0]);

       always @(posedge clk)
                {ns000,  ns001,  ns010,  ns011,  ns020,  ns021,  ns030, 
 ns031,  ns040,  ns041,  ns050,  ns051,  ns060,  ns061,  ns070,  ns071} = 
                reset ? {8'h64,  312'b0} : 
                {out000,  out001,  out010,  out011,  out020,  out021, 
 out030,  out031,  out040,  out041,  out050,  out051,  out060,  out061, 
 out070,  out071};

endmodule