testmyfifo.v

VERILOG HDL 实际工控项目源码

`include "myfifo.vo"
`timescale 1ns/1ns

module t;
reg we,wr_clk,rd_clk;
reg [3:0] page;
reg [13:0] data;
reg [6:0] wr_addr,rd_addr;

wire [16:0] d;	
reg [7:0] step;
initial 
begin
	we=1;
	wr_clk=0;
	rd_clk=0;
	page=0;
	
	for (step=0;step<=127;step=step+1)
	begin
	#5 wr_addr=step;
	#5 data='h100+step;
	#25 wr_clk=1;
	#25 wr_clk=0;
	#25 wr_clk=1;
	#25 wr_clk=0;
	end
	
	#200 we=0;
	

	for(step=0;step<=127;step=step+1)
	begin
	#0 rd_addr=step;
	page=4'hf;
	#20 rd_clk=1;
	#20 rd_clk=0;
	end
	

end



myfifo  m(.we(we),.page(page), .wr_clk(wr_clk), .rd_clk(rd_clk), .wr_addr(wr_addr),.rd_addr(rd_addr),  
					 .data(data), .d(d));

endmodule