mydram.v

VERILOG HDL 实际工控项目源码

// WARNING: Do NOT edit the input and output ports in this file in a text
// editor if you plan to continue editing the block that represents it in
// the Block Editor! File corruption is VERY likely to occur.

// Copyright (C) 1991-2004 Altera Corporation
// Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
// support information,  device programming or simulation file,  and any other
// associated  documentation or information  provided by  Altera  or a partner
// under  Altera's   Megafunction   Partnership   Program  may  be  used  only
// to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
// other  use  of such  megafunction  design,  netlist,  support  information,
// device programming or simulation file,  or any other  related documentation
// or information  is prohibited  for  any  other purpose,  including, but not
// limited to  modification,  reverse engineering,  de-compiling, or use  with
// any other  silicon devices,  unless such use is  explicitly  licensed under
// a separate agreement with  Altera  or a megafunction partner.  Title to the
// intellectual property,  including patents,  copyrights,  trademarks,  trade
// secrets,  or maskworks,  embodied in any such megafunction design, netlist,
// support  information,  device programming or simulation file,  or any other
// related documentation or information provided by  Altera  or a megafunction
// partner, remains with Altera, the megafunction partner, or their respective
// licensors. No other licenses, including any licenses needed under any third
// party's intellectual property, are provided herein.


// Generated by Quartus II Version 4.1 (Build Build 181 06/29/2004)
// Created on Wed Sep 01 11:17:48 2004

//  Module Declaration
module mydram
(
	// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
	rd_clk, wr_addr, page, rd_add, ad_db, strb, g_clk, rd_addr, ad_rd, 
	dram_busy, rst, dsp_rdy, d
	// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration

	// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	input rd_clk;
	input [6:0] wr_addr;
	input [3:0] page;
	input [15:12] rd_add;
	input [13:0] ad_db;
	input strb;
	input g_clk;
	input [7:0] rd_addr;
	input ad_rd;
	input dram_busy;
	input rst;
	output dsp_rdy;
	inout [15:0] d;
	// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!

wire rd_en ,rdy_en;
wire [7:0] rd , wr;

assign d=(~rd_en)? d_out : 16'hzzzz;

assign  rd_en=~rd_clk|strb|page[2]|(~rd_add[15])|rd_add[14]|(~rd_add[13])|(~rd_add[12]);
assign rdy_en=rd_clk|strb|page[2]|(~rd_add[15])|(~rd_add[14])|(~rd_add[13])|(~rd_add[12]);
wire [13:0] db;
assign db=ad_db^14'h2000 ;

reg [13:0] coll_mem [0:8];

always @(posedge g_clk)
begin
	if(ad_rd==0)
	coll_mem[wr_addr]<=db;
	coll_mem[8]<=rdy_reg;
end	

reg [13:0]d_out;
always @(rd_en)
begin
	if(rd_en==0)
	d_out<=coll_mem[rd_addr];
end



reg [13:0] rdy_reg;

always @(posedge rdy_en)
begin
	rdy_reg<=d;
end

reg dsp_rdy_en;
always @(posedge rst or posedge g_clk)
begin
	if(rst)
	begin
		dsp_rdy_en<=0;
	end
	else if(rdy_reg==14'h25a5)
		dsp_rdy_en<=1;
end
assign dsp_rdy=(~dram_busy)&dsp_rdy_en;
//assign dsp_rdy=(~ad_rd)&dsp_rdy_en;//test
endmodule