watchdog.v

VERILOG HDL 实际工控项目源码

// WARNING: Do NOT edit the input and output ports in this file in a text
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// Copyright (C) 1991-2004 Altera Corporation
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// support information,  device programming or simulation file,  and any other
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// to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
// other  use  of such  megafunction  design,  netlist,  support  information,
// device programming or simulation file,  or any other  related documentation
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// Generated by Quartus II Version 4.1 (Build Build 207 08/26/2004)
// Created on Mon Sep 06 09:32:31 2004

//  Module Declaration
module watchdog
(
	// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
	page, rd_add, rd_clk, g_clk, dog_en, strb, dsp_rst, rst, dir_4052
	// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration

	// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	input [3:0] page;
	input [15:12] rd_add;
	input rd_clk;
	input g_clk;
	input dog_en;
	input strb;
	output dsp_rst;
	output rst;
	output dir_4052;
	// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
	reg rst;
	wire feed_dog;
	
	assign dir_4052=dog_clk;
	assign feed_dog=strb|page[2]|(~rd_add[15])|(~rd_add[14])|(~rd_add[13])|rd_add[12];
	
	reg  [25:0] watch_reg;
	reg  [1:0] 	step;
	reg         dog_clk;
	
	always @(posedge rst or negedge feed_dog)
	if(rst)
	dog_clk<=0;
	else
		begin
			dog_clk=~dog_clk;
		end
	
	reg [1:0] dog_reg;
	always @(posedge rst or posedge g_clk)
	if(rst)
	dog_reg<=2'b00;
	else
		begin
			if(dog_en==0)
			dog_reg<=2'b10;
			else dog_reg<={dog_reg[0],dog_clk};
		end
		
	wire dog_end_en=^dog_reg;	
    always @(posedge g_clk)
	
	  begin
		 	case (step)
			
		 	0: begin
					rst<=0;
					step<=1;
				end
		 	1: begin
					rst<=1;
					step<=2;
				end	
		 	2: begin
				if(watch_reg>=25000000)
					begin
						watch_reg<=0;
						rst<=0;
						step<=3;
					end
				else watch_reg<=watch_reg+1;
				end
		 	3: begin
		 		if(dog_end_en)
					begin
			  		 watch_reg<=0;
			 		  rst<=0;
					end
				else if(watch_reg>=25000000)
				 	begin
					 	rst<=~rst;
						watch_reg<=0;
				 	end
         	 	 else  
					 begin
					 	watch_reg<=watch_reg+ 1;
				 	 end	
			end
			
		 endcase	
	  end
	assign dsp_rst=~rst;
endmodule