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lwbdecode.v
/////////////////////////////////////////////////////////////////////
//// ////
//// LWB rev 1.2 -- Memory Address Decode
sm.v
// Copyright Model Technology, a Mentor Graphics
// Corporation company 2003, - All rights reserved.
/*******************************
* Sample solution: - Synthesizable RTL
* - Separate signals,
and2.v
// Copyright Model Technology, a Mentor Graphics
// Corporation company 2003, - All rights reserved.
`timescale 1 ns / 1 ns
///////////////////////////////////////////////////
// and2 cell:
// W
set.v
// Copyright Model Technology, a Mentor Graphics
// Corporation company 2003, - All rights reserved.
`timescale 1ns/1ns
module cache_set(addr, data, hit, oen, wen);
input addr, oen, wen;
inout
memory.v
// Copyright Model Technology, a Mentor Graphics
// Corporation company 2003, - All rights reserved.
`timescale 1 ns / 1 ns
module memory(clk, addr, data, rw, strb, rdy);
input clk, addr, rw, s
gates.v
// Copyright Model Technology, a Mentor Graphics
// Corporation company 2003, - All rights reserved.
`timescale 1 ns / 1 ns
///////////////////////////////////////////////////
// and2 cell:
// W
top.v
// Copyright Model Technology, a Mentor Graphics
// Corporation company 2003, - All rights reserved.
`timescale 1 ns / 1 ns
module top;
reg clk;
// Processor bus signals
wire prw, pstrb, prdy
proc.v
// Copyright Model Technology, a Mentor Graphics
// Corporation company 2003, - All rights reserved.
`timescale 1 ns / 1 ns
module proc(clk, addr, data, rw, strb, rdy);
input clk, rdy;
outp
cache.v
// Copyright Model Technology, a Mentor Graphics
// Corporation company 2003, - All rights reserved.
`timescale 1 ns / 1 ns
module cache(clk, paddr, pdata, prw, pstrb, prdy,
saddr,
and2.v
// Copyright Model Technology, a Mentor Graphics
// Corporation company 2003, - All rights reserved.
`timescale 1 ns / 1 ns
///////////////////////////////////////////////////
// and2 cell:
// W