gates.v

来自「FPGA-CPLD_DesignTool,事例程序3-4」· Verilog 代码 · 共 50 行

// Copyright Model Technology, a Mentor Graphics
// Corporation company 2003, - All rights reserved.

`timescale 1 ns / 1 ns

///////////////////////////////////////////////////
// and2 cell:
//     Without the `celldefine compiler directive,
//     all internal primitives will be seen in the
//     dataflow window.
///////////////////////////////////////////////////
module and2 (input a, b,
             output y);

    buf (al, a);
    buf (bl, b);
    and (yl, al, bl);
    buf (y, yl);

    specify
        specparam t_rise = 1:1:1, t_fall = 1:1:1;
        (a => y) = (t_rise, t_fall);
        (b => y) = (t_rise, t_fall);
    endspecify

endmodule

///////////////////////////////////////////////////
// or2 cell:
//     This cell will be seen as a primitive since
//     it uses the `celldefine compiler directive.
///////////////////////////////////////////////////
`celldefine
module or2 (input a, b,
            output y);

    buf (al, a);
    buf (bl, b);
    or (yl, al, bl);
    buf (y, yl);

    specify
        specparam t_rise = 1:1:1, t_fall = 1:1:1;
        (a => y) = (t_rise, t_fall);
        (b => y) = (t_rise, t_fall);
    endspecify

endmodule
`endcelldefine