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dualportram.v
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: DualPortRAM.
top.v
module top(q, a, b, sel, r_l, clk, rst);
output [7:0] q;
input [7:0] a, b;
input sel, r_l, clk, rst;
wire [7:0] mux_out, reg_out;
mux mux_1 (.outvec(mux_out), .a_vec(a), .b_vec(b), .sel(sel));
mux.v
module mux (outvec, a_vec, b_vec, sel);
output[7:0] outvec;
input[7:0] a_vec, b_vec;
input sel;
mux21 u0 (.Y(outvec[0]), .A(a_vec[0]), .B(b_vec[0]), .SEL(sel));
mux21 u1 (.Y(outvec[1]), .A(a_ve
rotate.v
module rotate(q, data, clk, r_l, rst); // rotates bits or loads
output [7:0] q;
input [7:0] data;
input clk, r_l, rst;
reg [7:0] q;
// when r_l is high, it rotates; if low, it loads data
alway
alu.v
module alu(clk, a, b, opcode, outp);
input clk;
input [7:0] a, b;
input [2:0] opcode;
output [7:0] outp;
reg [7:0] outp;
always @(posedge clk)
begin
case (opcode) /* synthesis full_c
top.v
module top(q, a, b, sel, r_l, clk, rst);
output [7:0] q;
input [7:0] a, b;
input sel, r_l, clk, rst;
wire [7:0] mux_out, reg_out;
mux mux_1 (.outvec(mux_out), .a_vec(a), .b_vec(b), .sel(sel));
mux.v
module mux (outvec, a_vec, b_vec, sel);
output[7:0] outvec;
input[7:0] a_vec, b_vec;
input sel;
mux21 u0 (.Y(outvec[0]), .A(a_vec[0]), .B(b_vec[0]), .SEL(sel));
mux21 u1 (.Y(outvec[1]), .A(a_ve
rotate.v
module rotate(q, data, clk, r_l, rst); // rotates bits or loads
output [7:0] q;
input [7:0] data;
input clk, r_l, rst;
reg [7:0] q;
// when r_l is high, it rotates; if low, it loads data
alway
alu.v
module alu(clk, a, b, opcode, outp);
input clk;
input [7:0] a, b;
input [2:0] opcode;
output [7:0] outp;
reg [7:0] outp;
always @(posedge clk)
begin
case (opcode) /* synthesis full_c
sm.v
// Copyright Model Technology, a Mentor Graphics
// Corporation company 2003, - All rights reserved.
/*******************************
* Sample solution: - Synthesizable RTL
* - Separate signals,