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找到约 10,000 项符合
V 的代码
measure.v
module Measure(
Reset,
Start,
Clock,
InputWaveOne,
InputWaveTwo,
FreClockCounter,
FreWaveCounter,
PhaseClockCounter,
PhaseWaveCounter,
CountFinishFlag,
/* 20070818 */
IndicatorLight,
Ind
pll.v
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: PLL.v
// Megafunctio
frefindtable.v
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: FreFindTable
phasefindtable.v
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: PhaseFindTab
dds.v
module DDS
(
Clock,
FrequencyKey,
PhaseKey,
ClockOut,
WaveOutOne,
WaveOutTwo
);
input Clock;
input [21:0] FrequencyKey;
input [9:0] PhaseKey;
output ClockOut;
output [11:0] WaveOutOne;
o
strobe.v
module Strobe(SystemClock, DivideValue, VirtualClock);
input SystemClock;
input [27:0] DivideValue;
output VirtualClock;
//wire VirtualClock;
reg rVirtualClock;
assign VirtualClock = rVirtualC
adapter.v
module Adapter
(
Clock,
FrequencySet,
PhaseSet,
FrequencyKey,
PhaseKey
);
input Clock;
input [9:0] FrequencySet;
input [8:0] PhaseSet;
output [21:0] FrequencyKey;
output [9:0] PhaseKey;
accumulater.v
module Accumulater(Clock, Base, Increment);
input Clock;
output [29:0] Base;
input [21:0] Increment;
//wire Clock;
reg [29:0] Base;
wire [21:0] Increment;
//wire [31:0] temp;
//assign temp
workone.v
module TopLayer
(
/* 启动信号,系统时钟及待测信号输入 */
Reset,
MeasureStart,
SysClock,
WaveInOne,
WaveInTwo,
/* 频率和相位差预置及调节输入 */
Select,
Increase,
Decrease,
Double,
Halve,
/* 测量数据输出 */
ReadClock,
Dat
sinfindtable.v
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: SinFindTable