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V 的代码
parity.v
// Parity Generator
module parity(even_numbits, odd_numbits, input_bus);
output even_numbits, odd_numbits;
input [7:0] input_bus;
assign odd_numbits = ^ input_bus;
assign even_numbits = ~odd_
accum.v
module test (in1, in2, rst, out, clk);
parameter iw = 9;
parameter ow = iw*2 +1;
input [iw:0]in1, in2;
input rst, clk;
output [ow:0]out;
wire [ow:0]temp_mult;
reg [ow:0]out_reg;
assign
addmult.v
module test (in1, in2,in3, in4, rst, out, clk);
parameter iw = 9;
parameter ow = iw*2 +1;
input [iw:0]in1, in2, in3, in4;
input rst, clk;
output [ow:0]out;
wire [iw:0]add1;
wire [iw:0]add2;
sqrterr.v
`timescale 100ps/100ps
// Example that shows how to map logic into
// EABs for altera Flex10k devices.
//
// Compute an integer square root of an input
// bus of width 2n with a result bus s
myramv.v
`timescale 1ns / 1ns
module asyn_ram_16x16 (Q, Data,WE, Address); //synthesis black_box
input [15:0] Data;
input WE;
input [3:0] Address;
output [15:0] Q;
endmodule
module myramv(Q,Data,W
pad.v
// This example shows one how to force the
// use of a particular pad type for lucent.
module adder(cout, sum, a, b, cin);
parameter size = 1; /* declare a parameter. default required */
outpu
dff.v
// Simple flip-flop example without set or reset
module dff(q, data, clk);
output q /* synthesis dout="" */;
input data /* synthesis din="" */;
input clk;
reg q;
always @(posedge clk)
begi
smartcard.v
//******************************************************************
// (C) COPYRIGHT 2007 Southeast University ASIC Center
// ALL RIGHTS RESERVED
// File : SmartCard.v
// Author
timescale.v
`timescale 1ns / 1ns
timescale.v
`timescale 1ns/10ps