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div.v
/////////////////////////////////////////////////////////////////////
//// ////
//// Non-restoring singed dividor
icpld.v
// Quartus Verilog Template
// Counter with synchronous load and active low asynchronous clear
module icpld (
input [2:0] SWITCH_MODE,RAM_ADDR_LATCH,
input [3:0] RAM_DATA_SEL,MCU_CODE,
in
rcvr.v
`timescale 1 ns / 100ps
module rcvr ( clk,rst,rxd,baud_clk,baud_clk1,
fifor_cs,
data_out,EF,AE,AF,FF) ; //接收模块
input clk,rst ;
input baud_clk,baud_clk1;
input fifor_cs;
baud.v
`timescale 1ns/100ps
module baud(clk,rst,
baud_cs0,baud_cs1,baud_cs2,baud_cs3,
data,
baud_clk0,baud_clk1,baud_clk2,baud_clk3
);
input clk,rst;
input baud_cs0,bau
txmit.v
`timescale 1 ns / 100ps
module txmit ( clk,clk_in,rst,data,we,baud_clk,
sdo,EF,AE,AF,FF,we_en
) ; //发送模块
output sdo ;//serial data output
output EF,AE,AF,FF;
input [7
inter.v
`timescale 1ns/100ps
module inter( clk,csn,we,addr,data,
AE0,AF0,EF0,AE1,AF1,EF1,AE2,AF2,EF2,AE3,AF3,EF3,AF4,FF4,AF5,FF5,AF6,FF6,AF7,FF7,
inter_mask,inter //output
decode.v
`timescale 1ns/100ps
module decode( clk,addr,data,cs_n,we_n,oe_n,//input
baud_cs0,baud_cs1,baud_cs2,baud_cs3,
fifot0_cs,fifot1_cs,fifot2_cs,fifot3_cs,
fifor0_cs
timescale.v
`timescale 1ns / 1ns
timescale.v
`timescale 1ns/10ps
timescale.v
`timescale 1ns / 10ps