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`timescale 1ns/10ps /*----------------------------------------------------------------------------- $RCSfile: ppselect.v,v $ $Source: /home/lefurgy/tmp/ISC-repository/isc/hardware/ARM10/behavioral/pip

`timescale 1ns/10ps /***************************************************************************** $RCSfile: multacc.v,v $ $Revision: 1.1 $ $Author: kohlere $ $Date: 2000/03/24 01:52:16 $ $State: Exp

`timescale 1ns/10ps /***************************************************************************** $RCSfile: alu.v,v $ $Revision: 1.1 $ $Author: kohlere $ $Date: 2000/03/24 01:52:16 $ $State: Exp $ $S

`timescale 1ns/10ps /***************************************************************************** $RCSfile: pardef.v,v $ $Revision: 1.3 $ $Author: kohlere $ $Date: 2000/03/28 04:39:17 $ $State: Exp $

`timescale 1ns/10ps /***************************************************************************** $RCSfile: counters.v,v $ $Revision: 1.8 $ $Author: kohlere $ $Date: 2000/05/11 01:07:57 $ $State: Exp

`timescale 1ns/10ps module control(nGCLK, nWAIT, nRESET, DABORT, IABORT, nFIQ, nIRQ, ISYNC, CHSD, CHSE, ID, IA, irq_disable, fiq_disable, flags_ex, load_pc_me, exception_to_id, pc, inst_if,

`timescale 1ns/10ps `include "pardef" /***************************************************************************** $RCSfile: dcache.v,v $ $Revision: 1.15 $ $Author: kohlere $ $Date: 2000/05/04 16:31

`timescale 1ns/10ps `include "pardef" /***************************************************************************** $RCSfile: me.v,v $ $Revision: 1.5 $ $Author: kohlere $ $Date: 2000/04/17 18:12:50 $

`timescale 1ns/10ps /***************************************************************************** $RCSfile: decode.v,v $ $Revision: 1.1 $ $Author: kohlere $ $Date: 2000/04/10 18:17:59 $ $State: Exp $

`timescale 1ns/10ps `include "pardef" /***************************************************************************** $RCSfile: id.v,v $ $Revision: 1.10 $ $Author: kohlere $ $Date: 2000/04/17 18:12:50