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V 的代码
play.v
module play ( audio , sys_CLK );
output audio;
input sys_CLK;
reg [23:0] counter4Hz;
reg audiof;
always @(posedge sys_CLK) //4Hz分频
begin
if(counter4Hz==6250000) //6250000
did.v
module did(CLK,CLK_OUT);
input CLK;
output CLK_OUT;
reg CLK_OUT;
reg[5:0] num;
always@(posedge CLK)
begin
if(num
txd.v
//52分频
module txd(clk,txd,vcc);
input clk;
output txd;
output vcc;
reg [3:0] num;
reg [3:0] n;
reg txd;
assign vcc=1'b1;
always@(posedge clk)
begin
if(num==4'b0000)
begin
num=n
fft.v
/*
-- Arish Alreja: ECE 4902 Special Problems Spring 2006
-- School of Electrical & Computer Engineering
-- Georgia Institute of Technology
-- Atlanta, GA 30332
--
-- 64 point FFT Processor
--
--
timescale.v
`timescale 1ns / 10ps
v.bat
nasmw -otest.bin test.asm
ndisasmw test.bin >test.lst
IF exist test.bin goto hex:
echo shit
exit
:hex
echo OK
bin2hex test.bin >prom.mem.v
set path=c:\iverilog\bin
@rem iverilog -o
interleaver.v
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:15:32 08/12/2007
// Design Name:
/
timescale.v
`timescale 1ns / 10ps
lfsr.v
/////////////////////////////////////////////////////////////////////
//// ////
//// Linear Feedback Shift Register
dct.v
/////////////////////////////////////////////////////////////////////
//// ////
//// Discrete Cosine Transform, Parallel implementation