play.v

来自「通过VERILOG HDL语言使用CPLD连接PS2键盘」· Verilog 代码 · 共 19 行

module play (	audio , sys_CLK );
output  	audio;
input     	sys_CLK;
reg		[23:0] 		counter4Hz;
reg 				audiof;
always @(posedge sys_CLK) 		//4Hz分频
begin
	if(counter4Hz==6250000)	 		 //6250000
	begin
		counter4Hz=0;
		audiof=~audiof;
	end
	else
	begin
		counter4Hz=counter4Hz+1;
	end
end	
assign audio=audiof;  	
endmodule