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polyfilter.v
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:36:39 09/18/2007
// Design Name:
/
baker.v
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01:05:17 09/24/2007
// Design Name:
/
dedds.v
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:52:31 09/24/2007
// Design Name:
/
iir.v
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:44:13 09/23/2007
// Design Name:
/
adder.v
// megafunction wizard: %LPM_ADD_SUB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_add_sub
// ============================================================
// File Name: adder.v
//
boma.v
module boma(a,b,reset);
input [3:0]a;
input reset;
output [3:0]b;
reg [3:0]bb;
always @(a)
begin
if(reset==0)
begin
bb=0;
end
else
begin
bb=a;
end
end
assign b=bb;
endmodule
fashe.v
module fashe(clock,txd);
input clock;
output txd;
reg txd_reg;
reg [10:0] count;
reg [3:0] bitcnt_reg;
reg bit_start;
reg [7:0] uart_buf;
always @(posedge
hongwai.v
module hongwai(led,jie);
output [7:0]led;
input jie;
reg [7:0]ledd;
always@(jie)
begin
if(jie==0)
ledd=8'b11111111;
else
ledd=8'b10101010;
end
assign led=ledd;
endmodule
adc.v
module adc(clk,wr,rd,cs,shuchu,biaozhi,lddat,weixuan);
input [7:0] shuchu;
output [7:0] lddat;
input clk;
input biaozhi;
output rd;
output wr;
output cs;
output [2:0] weixuan;
reg rdd;
reg w
liushui.v
module liushui(clk,led,reset);
input clk;
input reset;
output[7:0] led;
reg[26:0] count;
reg[7:0] ledd;
always@ (posedge clk)
begin
if(reset==1)
begin
count=count+1;
end
else
count=0;
en