fashe.v

来自「通过VERILOG HDL语言使用CPLD连接PS2键盘」· Verilog 代码 · 共 50 行

module fashe(clock,txd);	
	input clock;
	output txd;
    
	reg txd_reg;					
	reg [10:0] count;				
	reg [3:0] bitcnt_reg;			
	reg bit_start;					
	reg [7:0] uart_buf;				

always @(posedge clock)
begin
	if (count<11'd1152)
	begin
		count=count+1;
		bit_start=0;
	end
	else
	begin
		count=0;
		bit_start=1;
	end
end
always @(posedge bit_start)
begin
     uart_buf=8'hff;
	if ( bitcnt_reg<4'd9)
		bitcnt_reg=bitcnt_reg+1;
	else
		bitcnt_reg=0;
	if(uart_buf != 8'd73)
	begin
	case (bitcnt_reg)
	  4'h0 : txd_reg=0 ;
	  4'h1 : txd_reg=uart_buf[0] ;
	  4'h2 : txd_reg=uart_buf[1] ;
	  4'h3 : txd_reg=uart_buf[2] ;
	  4'h4 : txd_reg=uart_buf[3] ;
	  4'h5 : txd_reg=uart_buf[4] ;
	  4'h6 : txd_reg=uart_buf[5] ;
	  4'h7 : txd_reg=uart_buf[6] ;
	  4'h8 : txd_reg=uart_buf[7] ;
	  4'h9 : txd_reg=1 ;
	  default : txd_reg=1 ;
	endcase
	end
end	
	
assign txd=txd_reg;	
endmodule