adc.v

通过VERILOG HDL语言使用CPLD连接PS2键盘

module adc(clk,wr,rd,cs,shuchu,biaozhi,lddat,weixuan);
input [7:0] shuchu;
output [7:0] lddat;
input clk;
input biaozhi;
output rd;
output wr;
output cs;
output [2:0] weixuan;
reg rdd;
reg wrr;
reg css;
reg [7:0] shuchuu;
reg [2:0] weixuann;
reg [7:0] lddat_reg;
reg [11:0] counter;
reg [4:0] count1;
reg [3:0] shuma;
reg EC;
reg nop;
reg nop1;
reg [1:0]state1;
reg [1:0]state2;
reg [11:0] count;
parameter	st0 = 2'b00,
            st1 = 2'b01,
            st2 = 2'b10,
			st3 = 2'b11;
always @ (posedge clk)
begin
state1=state2;
if(counter[11:0]==12'b101110111000)
begin
counter[11:0]=12'h000;
nop=1;
end
else
begin
counter=counter+1;
nop=0;
end
end
always @ (posedge clk)
begin
count1=count1+1;
if(count1==5'b11111)
begin
count1=5'b00000;
nop1=1;
end
else
nop1=0;
end
always @ ( state1 or biaozhi  )
begin
case(state1)
st0:begin
    css=1'b0;
    wrr=1'b0;
    rdd=1'b1;
    EC= 1'b0;
    if (nop1==1)
    begin
    state2 = st1;
    end
    else
    state2=st0;
    end 
st1:begin
    css=1'b1;
    wrr=1'b1;
    rdd=1'b1;
    EC= 1'b0;
    if(biaozhi==0)
    state2 = st2;
    else
    state2 = st1;
    end
st2:begin
    css=1'b0;
    wrr=1'b1;
    rdd=1'b0;
    EC= 1'b1;
    if (nop1==1)
    begin
    state2 = st3;
    end
    else
    state2=st2;
    end
st3:begin
    css=1'b1;
    wrr=1'b1;
    rdd=1'b1;
    EC=1'b0;
    state2= st0;    
    end
endcase
end
always @ (posedge clk) 
begin
if(EC==1)
shuchuu=shuchu;
end 
always @ (posedge clk)
begin
if(nop==0) 
begin
if(count<shuchuu)
begin
count=count+1;
if(count[3:0]>4'b1001)
begin
count[3:0]=4'b0000;
count[7:4]=count[7:4]+1;
end
if(count[7:4]>4'b1001)
begin
count[7:4]=4'b0000;
count[11:8]=count[11:8]+1;
end
end
end
else
begin
count=12'h000;
end
end
always @ (counter[11:10])
begin
case(counter[11:10])
2'b00:
begin
weixuann=001;
shuma=count[3:0];
end
2'b01:
begin
weixuann=010;
shuma=count[7:4];
end
2'b10:
begin
weixuann=100;
shuma=count[11:8];
end
endcase
end
always	@ (shuma)
	begin
		case(shuma)
			4'h0: lddat_reg = 8'hc0;
			4'h1: lddat_reg = 8'hf9;				//显示1
			4'h2: lddat_reg = 8'ha4;				//显示2
			4'h3: lddat_reg = 8'hb0;				//显示3
			4'h4: lddat_reg = 8'h99;				//显示4
			4'h5: lddat_reg = 8'h92;				//显示5
			4'h6: lddat_reg = 8'h82;				//显示6
			4'h7: lddat_reg = 8'hf8;				//显示7
			4'h8: lddat_reg = 8'h80;				//显示8
			4'h9: lddat_reg = 8'h90;				//显示9      
		endcase
	end
assign cs=css;
assign rd=rdd;
assign wr=wrr;
//assign led=shuchuu;
assign lddat=lddat_reg;
assign weixuan=weixuann;
endmodule