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resrcshr.v
// Without resource sharing you
// get an 8-bit adder and a 8-bit subtractor feeding a mux
module add_sub1(result, a, b, add_sub);
output [7:0] result;
input [7:0] a, b;
input add_sub;
reg [7:0]
scaleabl.v
// Creating a scaleable adder
module adder(cout, sum, a, b, cin);
parameter size = 1; /* declare a parameter. default required */
output cout;
output [size-1:0] sum; // sum uses the size para
sqrt.v
`timescale 100ps/100ps
//
// Compute an integer square root of an input
// bus of width 2n with a result bus size of n
//
module sqrtb(z, a);
parameter asize = 8;
output [(asize/2)-1:0] z;
inp
decoder.v
// 3-to-8 Decoder
module decoder(out, in);
output [7:0] out;
input [2:0] in;
assign out = 1'b1
compare.v
// Comparator
module compare(equal, a, b);
parameter size = 1;
output equal;
input [size-1:0] a, b; // declare inputs
assign equal = a == b;
endmodule
adder.v
// Creating a scaleable adder
module adder(cout, sum, a, b, cin);
parameter size = 1; /* declare a parameter. default required */
output cout;
output [size-1:0] sum; // sum uses the size para
mux.v
module mux(out, a, b, sel);
output out;
input a, b, sel;
reg out;
always @(a or b or sel)
begin
if (sel)
out = a;
else
out = b;
end
endmodule
bitand.v
module bitand(out, a, b);
output [3:0] out;
input [3:0] a, b;
/* this wire declaration is not required,
because out is an output in the port list */
wire [3:0] out;
assign out = a & b;
end
alu.v
// macro definitions for the opcodes
`define plus 3'd0
`define minus 3'd1
`define band 3'd2
`define bor 3'd3
`define unegate 3'd4
module alu(out, opcode, a, b);
output [7:0] out;
input [2:0
tristate.v
// Tri-state output driver example 1
module trist1(out, in, enable);
output out;
input in, enable;
assign out = enable ? in : 'bz;
endmodule
// Tri-state output driver example 2
m