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V 的代码
read.v
module Read
(
Reset,
StoreFlag,
MeasureStart,
SourceDataOne,
SourceDataTwo,
SourceDataThree,
SourceDataFour,
ReadClock,
OutBit,
ReadyFlag,
IndicatorLight
);
input Reset;
input StoreFlag
counter.v
`timescale 1ns/1ns
module counter( clk,
arst,
data
);
input clk; //input clock
input arst; //asynchronous res
seriesport.v
//模块名：series_port.v
`include "uart_defines.v"
module series_port (reset,clk,MC_BD,MC_BA,mc_cs3,fpa_rw,MC_re,mc_irq4,
lpd_txd,ltp_txd,tpm_txd,outer_txd,
tcounter.v
module test_counter;
reg clk, rst;
wire [7:0] count;
counter #(5,10) dut (count,clk,rst);
initial // Clock generator
begin
clk = 0;
#10 forever #10 clk = !clk;
end
initi
counter.v
module counter (count, clk, reset);
output [7:0] count;
input clk, reset;
reg [7:0] count;
parameter tpd_clk_to_count = 1;
parameter tpd_reset_to_count = 1;
function [7:0] increment;
tcounter.v
module test_counter;
reg clk, rst;
wire [7:0] count;
counter #(5,10) dut (count,clk,rst);
initial // Clock generator
begin
clk = 0;
#10 forever #10 clk = !clk;
end
initi
counter.v
module counter (count, clk, reset);
output [7:0] count;
input clk, reset;
reg [7:0] count;
parameter tpd_clk_to_count = 1;
parameter tpd_reset_to_count = 1;
function [7:0] increment;
top.v
// Copyright (C) 1991-2004 Altera Corporation
// Any megafunction design, and related netlist (encrypted or decrypted),
// support information, device programming or simulation file, and any
top.v
// Copyright (C) 1991-2004 Altera Corporation
// Any megafunction design, and related netlist (encrypted or decrypted),
// support information, device programming or simulation file, and any
dualportram.v
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: DualPortRAM.