read.v

Verilog实现的DDS正弦信号发生器和测频测相模块

module Read
(
Reset,
StoreFlag,
MeasureStart,
SourceDataOne,
SourceDataTwo,
SourceDataThree,
SourceDataFour,
ReadClock,
OutBit,
ReadyFlag,
IndicatorLight
);
input Reset;
input StoreFlag;
input MeasureStart;
input [31:0] SourceDataOne;
input [31:0] SourceDataTwo;
input [31:0] SourceDataThree;
input [31:0] SourceDataFour;
input ReadClock;
output OutBit;
output ReadyFlag;
output IndicatorLight;

reg rIndicatorLight;
assign IndicatorLight = rIndicatorLight;

reg rReadyFlag;
assign ReadyFlag = rReadyFlag;

reg [127:0] SourceData;
reg [6:0] Counter;
reg tempbit;
assign OutBit = tempbit;

//reg rClear;
//assign Clear = rClear;

always @ (posedge Reset or posedge ReadClock)
begin
  if (1 == Reset)
  begin 
    tempbit <= 0;
    Counter <= 7'd0;
  end
  else
  begin
    tempbit <= SourceData[127 - Counter];
    Counter <= Counter + 7'd1;
  end
end


//always @ (posedge Reset or posedge StoreFlag or posedge ReadClock)
always @ (posedge Reset or posedge MeasureStart or posedge StoreFlag)
begin
  if (1 == Reset)
  begin 
    rReadyFlag <= 0;
    rIndicatorLight <= 1;
    SourceData <= 128'd0;
	//rClear <= 0;
    //tempbit <= 0;
    //Counter <= 7'd0;
  end
  else if (1 == MeasureStart)
  begin
    rReadyFlag <= 0;
    rIndicatorLight <= 1;
    SourceData <= 128'd0;
  end
  else //if (1 == StoreFlag)
  begin 
    SourceData[31:0] <= SourceDataOne;
    SourceData[63:32] <= SourceDataTwo;
    SourceData[95:64] <= SourceDataThree;
    SourceData[127:96] <= SourceDataFour; 
    rReadyFlag <= 1;
    rIndicatorLight <= 0;
    //rClear <= 0;
  end
//  else if (0 == StoreFlag)
//  begin
//    rReadyFlag <= 0;
//    rIndicatorLight <= 1;
//  end
  
//  else //if (1 == ReadClock)
//  begin
//    //tempbit = SourceData[127 - Counter];
////    tempbit = SourceData[127];
////    SourceData = SourceData<<1;
////    Counter = Counter + 7'd1;
//    
//    if (7'd127 == Counter)
//    begin
//      rClear <= 1;
//      rReadyFlag <= 0;
//      rIndicatorLight <= 1;
//    end 
//  end
end

endmodule