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sgate.v
// Copyright (C) 1988-2002 Altera Corporation
// Any megafunction design, and related netlist (encrypted or decrypted),
// support information, device programming or simulation file, and any
sgate.v
// Copyright (C) 1988-2002 Altera Corporation
// Any megafunction design, and related netlist (encrypted or decrypted),
// support information, device programming or simulation file, and any
enc.v
// megafunction wizard: %8B10B Encoder/Decoder v1.4.0%
// ============================================================
// Megafunction Name(s):
// ENC_aot1151_enc8b10b
// ====================
enc.v
// megafunction wizard: %8B10B Encoder/Decoder v1.4.0%
// ============================================================
// Megafunction Name(s):
// ENC_aot1151_enc8b10b
// ====================
smallcntr.v
module smallcntr(CE,CLK,CLR,QOUT);
input CE;
input CLK;
input CLR;
output [3:0] QOUT;
reg [3:0] QOUT;
always@(posedge CLK or posedge CLR)
begin
if(CLR)
QOUT = 4'b0000;
else if(CE
tenths.v
/*******************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation o
stopwatch.v
module stopwatch(CLK, RESET, STRTSTOP, TENTHSOUT, ONESOUT, TENSOUT);
input CLK;
input RESET;
input STRTSTOP;
output [9:0] TENTHSOUT;
output [6:0] ONESOUT;
output [6:0] TENSOUT;
wire strtstopinv;
wir
statmach.v
module statmach(CLK,RESET,STRTSTOP,CLKEN,RST);
input CLK;
input RESET;
input STRTSTOP;
output CLKEN;
output RST;
reg CLKEN;
reg RST;
parameter [5:0] //synopsys enum STATE_TYPE
clear=6'
decode.v
module decode (ONE_HOT, BINARY);
input [3:0] BINARY;
output [9:0] ONE_HOT;
reg [9:0] ONE_HOT;
always@(BINARY)
case (BINARY)
4'b0001 : ONE_HOT = 10'b0000000001; // 1
4'b0010 : ONE_HOT =
smallcntr.v
module smallcntr(CE,CLK,CLR,QOUT);
input CE;
input CLK;
input CLR;
output [3:0] QOUT;
reg [3:0] QOUT;
always@(posedge CLK or posedge CLR)
begin
if(CLR)
QOUT = 4'b0000;
else if(CE