stopwatch.v

来自「FPGA-CPLD_DesignTool(example7）」· Verilog 代码 · 共 55 行

module stopwatch(CLK, RESET, STRTSTOP, TENTHSOUT, ONESOUT, TENSOUT);

input CLK;
input RESET;
input STRTSTOP;
output [9:0] TENTHSOUT;
output [6:0] ONESOUT;
output [6:0] TENSOUT;

wire strtstopinv;
wire clkenable;
wire rstint;
wire [9:0] xcountout;
wire xtermcnt;
wire cnt60enable;
wire [3:0] lsbcnt;
wire [3:0] msbcnt;
wire [3:0] Q;

statmach MACHINE(.CLK(CLK),
		 .RESET(RESET),
		 .STRTSTOP(STRTSTOP),
		 .CLKEN(clkenable),
		 .RST(rstint));

//Place the CoreGen Component Instantiation for Tenths here
tenths XCOUNTER (
		.Q(Q),
		.CLK(CLK),
		.Q_THRESH0(xtermcnt),
		.CE(clkenable),
		.AINIT(rstint));
//------ End INSTANTIATION Template ---------

decode one_decode (.BINARY(Q), .ONE_HOT(xcountout));
	
cnt60 sixty(.CE(cnt60enable),
		    .CLK(CLK),
		    .CLR(rstint),
	   	 .LSBSEC(lsbcnt),
			 .MSBSEC(msbcnt));

hex2led lsbled(.HEX(lsbcnt),.LED(ONESOUT));
hex2led msbled(.HEX(msbcnt),.LED(TENSOUT));

assign cnt60enable = xtermcnt & clkenable;
assign TENTHSOUT = ~xcountout;
assign strtstopinv = ~STRTSTOP;

endmodule