statmach.v

来自「FPGA-CPLD_DesignTool(example7）」· Verilog 代码 · 共 70 行

module statmach(CLK,RESET,STRTSTOP,CLKEN,RST);

input CLK;
input RESET;
input STRTSTOP;
output CLKEN;
output RST;

reg CLKEN;
reg RST;
   
   
parameter [5:0] //synopsys enum STATE_TYPE
      clear=6'b000001,
       zero=6'b000010,
      start=6'b000100,
   counting=6'b001000,
      stop1=6'b010000,
    stopped=6'b100000;
   
reg [5:0] 	/* synopsys enum STATE_TYPE */ current_state; 
reg [5:0] 	/* synopsys enum STATE_TYPE */ next_state;

   always@(current_state or STRTSTOP)
      begin
	 case(current_state) //synopsys full_case parallel_case
	 		clear:begin
				next_state<=zero;
		    	CLKEN<=1'b0;
		    	RST<=1'b1;
		   end
	      zero:begin
		    	next_state<=(STRTSTOP)?start:zero;
		    	CLKEN<=1'b0;
		    	RST<=1'b0;		    
		   end
	      start:begin
		   	next_state<=(STRTSTOP)?start:counting;
		    	CLKEN<=1'b0;
		    	RST<=1'b0;		    		 
		   end
	   	counting:begin
	      	next_state<=(STRTSTOP)?stop1:counting;
		    	CLKEN<=1'b1;
		    	RST<=1'b0;		    		 	      
	      end
	      stop1:begin
		    	next_state<=(STRTSTOP)?stop1:stopped;
		    	CLKEN<=1'b0;
		    	RST<=1'b0;
	      end
	    	stopped:begin
	         next_state<=(STRTSTOP)?start:stopped;
		    	CLKEN<=1'b0;
		    	RST<=1'b0;	       
	      end
	 endcase
   end
   
   always@(posedge CLK or posedge RESET)
      begin
		 if(RESET==1'b1)
	    	current_state = clear;
	 	 else
	    	current_state = next_state;
       end
   
endmodule