counter.v

来自「一本老师推荐的经典的VHDL覆盖基础的入门书籍」· Verilog 代码 · 共 24 行

`timescale 1ns/1ns
module counter( clk,
                arst,
                data	        
                );


 input          clk;   //input clock
 input          arst;   //asynchronous reset, low effect
 
 output [7:0]   data;
 reg    [7:0]   data;

 


always@(posedge clk or negedge arst)	
     if(!arst)
	data <= 0;
     else
        data <= data+1;


endmodule