📄 spiprocess.v
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module spiprocess(clk,cpurd,cpuwr,cpusel,cpuindata,ramindata,outdata,addr,mosi,miso,reset,irq,CSN,SCK,RFirq,SendAddr,SendRDen,ReceiveData,ReceiveAddr,SendramCLK,ReceiveCLK,ReceiveWen,CE,sendfinishtest);
input reset;
input clk;
input cpurd;
input cpuwr;
input cpusel;
input [7:0] cpuindata;
input [11:0] addr;
input miso;
input RFirq;
input [7:0] ramindata;
output [7:0] outdata;
output mosi;
output irq;
output CSN;
output SCK;
output [5:0] SendAddr;
output SendRDen;
output [7:0] ReceiveData;
output [5:0] ReceiveAddr;
output SendramCLK;
output ReceiveCLK;
output ReceiveWen;
output CE;
output sendfinishtest;
reg [7:0] outdata;
reg mosi;
reg irq;
reg CSN;
reg SCK;
reg [5:0] SendAddr;
reg SendRDen;
reg [7:0] ReceiveData;
reg [5:0] ReceiveAddr;
reg SendramCLK;
reg ReceiveCLK;
reg ReceiveWen;
reg CE;
reg sendfinishtest;
reg [7:0] Receivedata;
reg [5:0] SendByteNum;
reg [7:0] StatusReg0;
reg [7:0] StatusReg1;
reg [7:0] StatusReg2;
reg [7:0] StatusReg3;
reg [7:0] StatusReg4;
reg senden;
reg sendfilish;
reg [5:0] sendFinishByte;
reg [5:0] receiveByte;
reg ReadReging;
reg [4:0] bitcounter;
reg [7:0] senddata;
reg [7:0] ramsendtemp;
reg [7:0] ramdReceivetemp;
reg ready;
reg [2:0] RegNum;
reg [7:0] RegAddr0;
reg [7:0] RegAddr1;
reg [7:0] RegAddr2;
reg [7:0] RegAddr3;
reg [7:0] RegAddr4;
reg senddatastart;
reg ReceiveReady;
reg ReceiveReady1;
reg ReceiveReady2;
reg ReceiveReady3;
reg ReceiveReady4;
reg ReceivesomeData;
reg T_ReceivesomeData1;
reg T_ReceivesomeData2;
reg T_ReceivesomeData3;
reg T_ReceivesomeData4;
reg T_ReceivesomeData5;
reg T_ReceivesomeData6;
always @(negedge cpurd)
begin
if(cpusel==0)
case(addr) //0x880~0x88f
12'b100010000000: outdata[7:0]=StatusReg0;
12'b100010000001: outdata[7:0]=StatusReg1;
12'b100010000010: outdata[7:0]=StatusReg2;
12'b100010000011: outdata[7:0]=StatusReg3;
12'b100010000100: outdata[7:0]=StatusReg4;
12'b100010000101: outdata[5:0]=receiveByte[5:0];
12'b100010000110: outdata[0]=sendfilish;
12'b100010000111: outdata[0]=ReceivesomeData;
12'b100010001000: T_ReceivesomeData5=~T_ReceivesomeData5;
endcase
end
always @(posedge cpuwr)
begin
if(~reset)
begin
SendByteNum=6'b0;
senden=1'b0;
CE=1'b1;
RegAddr1=8'b00000001;
RegAddr2=8'b00000010;
RegAddr3=8'b00000011;
RegAddr4=8'b00000100;
end
else
if(cpusel==0)
case(addr) // 0x8c0~0x8cf
12'b100011000000: CE=cpuindata[0];
12'b100011000001: RegAddr1=cpuindata;
12'b100011000010: RegAddr2=cpuindata;
12'b100011000011: RegAddr3=cpuindata;
12'b100011000100: RegAddr4=cpuindata;
12'b100011001000:
begin
SendByteNum[5:0]=cpuindata[5:0]; //发送的字节数
senden=~senden;
end
endcase
end
/*
always @(posedge RFirq)
begin
T_ReceivesomeData1=~T_ReceivesomeData1;
end
*/
always @(negedge RFirq)
begin
T_ReceivesomeData2=~T_ReceivesomeData2;
end
always @(posedge clk)
begin
if(~reset)
begin
T_ReceivesomeData3=T_ReceivesomeData1;
T_ReceivesomeData4=T_ReceivesomeData2;
ReceivesomeData=1'b0;
T_ReceivesomeData6=T_ReceivesomeData5;
sendfinishtest=1'b1;
end
else
begin
/*
if(T_ReceivesomeData3!=T_ReceivesomeData1)
begin
T_ReceivesomeData3=T_ReceivesomeData1;
ReceivesomeData=1'b1;
end
else
*/
if (T_ReceivesomeData4!=T_ReceivesomeData2)
begin
T_ReceivesomeData4=T_ReceivesomeData2;
ReceivesomeData=1'b0;
end
else if(T_ReceivesomeData6!=T_ReceivesomeData5)
begin
T_ReceivesomeData6=T_ReceivesomeData5;
ReceivesomeData=1'b1;
end
sendfinishtest=ReceivesomeData;
end
end
always @(posedge clk)
begin
if(~reset)
begin
mosi=1'b0;
irq=1'b0;
CSN=1'b1;
SCK=1'b0;
sendfilish=1'b1;
StatusReg0=8'b0;
ReadReging=1'b0;
sendFinishByte=6'b0;
bitcounter=5'b0;
senddata=8'b11111111;
ready=1'b0;
ReceiveAddr=6'b0;
SendAddr=6'b0;
RegNum=3'b0;
ReceiveWen=1'b0;
SendRDen=1'b0;
senddatastart=senden;
StatusReg0=8'b0;
StatusReg1=8'b11111111;
StatusReg2=8'b0;
StatusReg3=8'b11111111;
StatusReg4=8'b0;
ReceiveReady=1'b0;
end
else
begin
irq=~RFirq;
if((senddatastart==~senden)&&(ReadReging==0)) //如果有数据发送并且不处于正在读射频寄存器的状态中，那么就发送数据
begin
if(sendFinishByte<SendByteNum) //判断是否将数据发送完
begin
if(sendFinishByte==0) //发送第一个字节
begin
receiveByte=6'b0;
if(ready==1'b0)
begin
case(bitcounter)
5'b00000:
begin
sendfilish=1'b0; //标记，处于发送状态中
SendRDen=1'b1;
SendAddr=6'b0;
SendramCLK=1'b0;
bitcounter=bitcounter+5'b1;
end
5'b00001:
begin
SendramCLK=1'b1;
bitcounter=bitcounter+5'b1;
end
5'b00010:
begin
SendramCLK=1'b0;
ramsendtemp=ramindata; //读取第一个发送数据
senddata=ramsendtemp;
bitcounter=bitcounter+5'b1;
SendAddr=SendAddr+6'b1;
end
5'b00011:
begin
// SendramCLK=1'b1;
// ramsendtemp=ramindata;
// senddata=ramsendtemp;
bitcounter=5'b0;
ready=1'b1;
SendRDen=1'b0;
end
endcase
end
else if(ready==1)
begin
case(bitcounter)
5'b00000:
begin
CSN=1'b0;
SCK=1'b0;
mosi=senddata[7];
bitcounter=bitcounter+5'b1;
SendRDen=1'b1;
SendramCLK=1'b0;
end
5'b00001:
begin
SCK=1'b1;
StatusReg0[7]=miso;
bitcounter=bitcounter+5'b1;
SendramCLK=1'b1;
end
5'b00010:
begin
SCK=1'b0;
mosi=senddata[6];
bitcounter=bitcounter+5'b1;
ramsendtemp=ramindata; //读取下一个数据
end
5'b00011:
begin
SCK=1'b1;
StatusReg0[6]=miso;
bitcounter=bitcounter+5'b1;
SendramCLK=1'b0;
SendRDen=1'b0; //Read
SendAddr=SendAddr+6'b1;
end
5'b00100:
begin
SCK=1'b0;
mosi=senddata[5];
bitcounter=bitcounter+5'b1;
end
5'b00101:
begin
SCK=1'b1;
StatusReg0[5]=miso;
bitcounter=bitcounter+5'b1;
end
5'b00110:
begin
SCK=1'b0;
mosi=senddata[4];
bitcounter=bitcounter+5'b1;
end
5'b00111:
begin
SCK=1'b1;
StatusReg0[4]=miso;
bitcounter=bitcounter+5'b1;
end
5'b01000:
begin
SCK=1'b0;
mosi=senddata[3];
bitcounter=bitcounter+5'b1;
end
5'b01001:
begin
SCK=1'b1;
StatusReg0[3]=miso;
bitcounter=bitcounter+5'b1;
end
5'b01010:
begin
SCK=1'b0;
mosi=senddata[2];
bitcounter=bitcounter+5'b1;
end
5'b01011:
begin
SCK=1'b1;
StatusReg0[2]=miso;
bitcounter=bitcounter+5'b1;
end
5'b01100:
begin
SCK=1'b0;
mosi=senddata[1];
bitcounter=bitcounter+5'b1;
end
5'b01101:
begin
SCK=1'b1;
StatusReg0[1]=miso;
bitcounter=bitcounter+5'b1;
end
5'b01110:
begin
SCK=1'b0;
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