test.map.summary

来自「用fpga实现isp接口的源码」· SUMMARY 代码 · 共 11 行

Analysis & Synthesis Status : Successful - Fri Dec 01 16:33:51 2006
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Web Edition
Revision Name : TEST
Top-level Entity Name : TEST
Family : Cyclone
Total logic elements : 1,344
Total pins : 49
Total virtual pins : 0
Total memory bits : 512
Total PLLs : 0