block.v

viterbi译码器的一种fpga实现

`include "defs.h"

module block(sum_enc_bits0,  sub_enc_bits0,  sum_enc_bits1, 
 sub_enc_bits1,  sum_enc_bits2,  sub_enc_bits2,  
             sum_enc_bits3,  sub_enc_bits3,  sum_enc_bits4, 
 sub_enc_bits4,  sum_enc_bits5,  sub_enc_bits5,  cmp,  reset,  clk);

input            reset,  clk;
input   [4-1:0] sum_enc_bits0,  sub_enc_bits0,  sum_enc_bits1, 
 sub_enc_bits1,  sum_enc_bits2,  sub_enc_bits2,  
             sum_enc_bits3,  sub_enc_bits3,  sum_enc_bits4, 
 sub_enc_bits4,  sum_enc_bits5,  sub_enc_bits5;
output  [48-1:0] cmp;
wire    [`W-1:0] out000,  out001,  out010,  out011,  out020,  out021, 
 out030,  out031,  out040,  out041,  out050,  out051,  out060,  out061, 
 out070,  out071, 
                 out100,  out101,  out110,  out111,  out120,  out121, 
 out130,  out131,  out140,  out141,  out150,  out151,  out160,  out161, 
 out170,  out171, 
                 out200,  out201,  out210,  out211,  out220,  out221, 
 out230,  out231,  out240,  out241,  out250,  out251,  out260,  out261, 
 out270,  out271, 
                 out300,  out301,  out310,  out311,  out320,  out321, 
 out330,  out331,  out340,  out341,  out350,  out351,  out360,  out361, 
 out370,  out371, 
                 out400,  out401,  out410,  out411,  out420,  out421, 
 out430,  out431,  out440,  out441,  out450,  out451,  out460,  out461, 
 out470,  out471, 
                 out500,  out501,  out510,  out511,  out520,  out521, 
 out530,  out531,  out540,  out541,  out550,  out551,  out560,  out561, 
 out570,  out571;
reg     [`W-1:0] ns500,  ns501,  ns510,  ns511,  ns520,  ns521,  ns530, 
 ns531,  ns540,  ns541,  ns550,  ns551,  ns560,  ns561,  ns570,  ns571;

stage  st0(ns500,  ns511,  ns530,  ns521,  ns550,  ns541,  ns560,  ns571, 
 ns510,  ns501,  ns520,  ns531,  ns540,  ns551,  ns570,  ns561, 
         sum_enc_bits0,  sub_enc_bits0, 
         out000,  out001,  out010,  out011,  out020,  out021,  out030, 
 out031,  out040,  out041,  out050,  out051,  out060,  out061,  out070, 
 out071,  cmp[7:0]);
stage  st1(out000,  out011,  out030,  out021,  out050,  out041,  out060, 
 out071,  out010,  out001,  out020,  out031,  out040,  out051,  out070, 
 out061, 
         sum_enc_bits1,  sub_enc_bits1, 
         out100,  out101,  out110,  out111,  out120,  out121,  out130, 
 out131,  out140,  out141,  out150,  out151,  out160,  out161,  out170, 
 out171,  cmp[15:8]);
stage  st2(out100,  out111,  out130,  out121,  out150,  out141,  out160, 
 out171,  out110,  out101,  out120,  out131,  out140,  out151,  out170, 
 out161, 
         sum_enc_bits2,  sub_enc_bits2, 
         out200,  out201,  out210,  out211,  out220,  out221,  out230, 
 out231,  out240,  out241,  out250,  out251,  out260,  out261,  out270, 
 out271,  cmp[23:16]);
stage  st3(out200,  out211,  out230,  out221,  out250,  out241,  out260, 
 out271,  out210,  out201,  out220,  out231,  out240,  out251,  out270, 
 out261, 
         sum_enc_bits3,  sub_enc_bits3, 
         out300,  out301,  out310,  out311,  out320,  out321,  out330, 
 out331,  out340,  out341,  out350,  out351,  out360,  out361,  out370, 
 out371,  cmp[31:24]);
stage  st4(out300,  out311,  out330,  out321,  out350,  out341,  out360, 
 out371,  out310,  out301,  out320,  out331,  out340,  out351,  out370, 
 out361, 
         sum_enc_bits4,  sub_enc_bits4, 
         out400,  out401,  out410,  out411,  out420,  out421,  out430, 
 out431,  out440,  out441,  out450,  out451,  out460,  out461,  out470, 
 out471,  cmp[39:32]);
stage  st5(out400,  out411,  out430,  out421,  out450,  out441,  out460, 
 out471,  out410,  out401,  out420,  out431,  out440,  out451,  out470, 
 out461, 
         sum_enc_bits5,  sub_enc_bits5, 
         out500,  out501,  out510,  out511,  out520,  out521,  out530, 
 out531,  out540,  out541,  out550,  out551,  out560,  out561,  out570, 
 out571,  cmp[47:40]);

       always @(posedge clk)
                {ns500,  ns501,  ns510,  ns511,  ns520,  ns521,  ns530, 
 ns531,  ns540,  ns541,  ns550,  ns551,  ns560,  ns561,  ns570,  ns571} = 
                reset ? {8'h64,  184'b0} : 
                {out500,  out501,  out510,  out511,  out520,  out521, 
 out530,  out531,  out540,  out541,  out550,  out551,  out560,  out561, 
 out570,  out571};

endmodule