decoder.v

viterbi译码器的一种fpga实现

`include "defs.h"

module decoder(encoded_signal, bit_line, reset, clk);

input  [16-1:0] encoded_signal;
input           reset;
output [3:0]  bit_line;

input clk;

wire  [`S-1:0] sum_enc_bits0, sub_enc_bits0, sum_enc_bits1, sub_enc_bits1;
wire  [8-1:0] cmp;
reg   [8-1:0] cmp0, cmp1, cmp2;
reg   [16-1:0] b_cmp0, b_cmp1;
wire  restart;

block blk(sum_enc_bits0, sub_enc_bits0, sum_enc_bits1, sub_enc_bits1, cmp, reset, clk);

backtrack bt(b_cmp0, restart, clk, bit_line);

assign sum_enc_bits0 = encoded_signal[15:12] + encoded_signal[11:8];
assign sub_enc_bits0 = encoded_signal[15:12] - encoded_signal[11:8];
assign sum_enc_bits1 = encoded_signal[7:4] + encoded_signal[3:0];
assign sub_enc_bits1 = encoded_signal[7:4] - encoded_signal[3:0];

always @(posedge clk) cmp2 = #5 cmp1;
always @(posedge clk) cmp1 = #5 cmp0;
always @(posedge clk) cmp0 = #5 cmp;

always @(posedge clk) b_cmp0 = #5 restart == 1 ? {cmp , cmp0} : b_cmp1;
always @(posedge clk) b_cmp1 = #5 {cmp1, cmp2};

reg cnt;
assign restart = cnt == 1;
always @(posedge clk)
       if (reset == 1) cnt = 0;
       else if (cnt == 1) cnt = 0;
            else cnt = cnt + 1;

endmodule