backtrack.v

viterbi译码器的一种fpga实现

`include "defs.h"

module backtrack(cmp,  restart,  clk, 
             bit_line);

input   [16-1:0] cmp;
input   restart,  clk;
output  [1:0] bit_line;

wire    out000,  out001,  out010,  out011,  out020,  out021,  out030, 
 out031,  out040,  out041,  out050,  out051,  out060,  out061,  out070, 
 out071, 
                 out100,  out101,  out110,  out111,  out120,  out121, 
 out130,  out131,  out140,  out141,  out150,  out151,  out160,  out161, 
 out170,  out171;

reg    [15:0]last_out;
always @(posedge clk) last_out = {out100,  out101,  out110, 
 out111,  out120,  out121,  out130,  out131,  out140,  out141,  out150, 
 out151,  out160,  out161,  out170,  out171};
reg del_restart;
always @(posedge clk) del_restart = restart;
wire   [15:0]first_in = del_restart == 1 ? {1'b1,  1'b0,  1'b0, 
 1'b0,  1'b0,  1'b0,  1'b0,  1'b0,  1'b0,  1'b0,  1'b0,  1'b0,  1'b0,  1'b0,  1'b0, 
 1'b0} : last_out;

MS_res_stage  st0(cmp[7:0],  bit_line[0], 
         out100,  out111,  out130,  out121,  out150,  out141,  out160, 
 out171,  out110,  out101,  out120,  out131,  out140,  out151,  out170, 
 out161, 
         out000,  out001,  out010,  out011,  out020,  out021,  out030, 
 out031,  out040,  out041,  out050,  out051,  out060,  out061,  out070, 
 out071);
MS_res_stage  st1(cmp[15:8],  bit_line[1], 
         out000,  out011,  out030,  out021,  out050,  out041,  out060, 
 out071,  out010,  out001,  out020,  out031,  out040,  out051,  out070, 
 out061, 
         first_in[15],  first_in[14],  first_in[13],  first_in[12], 
 first_in[11],  first_in[10],  first_in[9],  first_in[8], 
 first_in[7],  first_in[6],  first_in[5],  first_in[4],  first_in[3], 
 first_in[2],  first_in[1],  first_in[0]);

endmodule